Elective Microprocessor

MicroprocessorUnit 814 min read

Evolution of Microprocessors & Short Notes: 8085→8086→Modern CPUs, Interrupts, DMA, USART, Flags

Unit 8 of Microprocessor covers the historical progression from 8085 to modern CPUs, key differences between microprocessors and microcontrollers, and short notes on critical components like interrupts, DMA, USART, and flag registers—essential for understanding system architecture and performance trade-offs.

TAKEAWAYS

  • Evolution timeline: 8085 (8-bit, 5 MHz) → 8086 (16-bit, pipelined) → Pentium (32-bit, superscalar) → modern CPUs (64-bit, multi-core, out-of-order execution).
  • Microprocessor vs. Microcontroller: Microprocessors need external memory/peripherals; microcontrollers integrate memory, timers, and I/O on-chip (ideal for embedded systems).
  • Interrupts vs. DMA: Interrupts (software-driven) handle events via ISRs; DMA (hardware-driven) transfers data directly between peripherals and memory without CPU intervention.
  • USART/Serial Communication: Asynchronous serial protocols (RS-232, UART) enable long-distance communication (e.g., modems, GPS modules) via start/stop bits and parity.
  • Flag Registers: 8086’s 16-bit flags (e.g., CF, ZF, SF) control program flow (e.g., loops, jumps) based on arithmetic/logic outcomes.
  • Real-world impact: Modern CPUs use pipelining (like 8086’s BIU/EU split) and DMA (e.g., in eSewa’s payment processing or Pathao’s GPS data streaming) to optimize performance.

1. Evolution of Microprocessors: From 8085 to Modern CPUs

1.1 Key Generations and Milestones

Microprocessors evolved to meet demands for speed, efficiency, and functionality. Below is a timeline with architectural breakthroughs:

19748085 (Intel) -8-bit, 5 MHz, 64KB add19788086 (Intel) -16-bit, pipelined (BIU198580386 (Intel) -32-bit, virtual memory1993Pentium (Intel) -Superscalar (multiple 2000Pentium 4 -Hyper-Threading (simul2005Core Duo (Intel) -First true multi-core 2010ARM Cortex-A(Mobile) - Low-power, 2020Apple M1(ARM-based) - Unified
Key milestones in microprocessor evolution (simplified timeline)

1.2 Architectural Advancements

Feature 8085 8086 Modern CPUs (e.g., Intel Core i7)
Bit-width 8-bit 16-bit 64-bit (x86-64)
Clock Speed 5 MHz 5–10 MHz 3–5 GHz (turbo boost)
Address Bus 16-bit (64KB) 20-bit (1MB) 48–64-bit (16EB)
Data Bus 8-bit 16-bit 64-bit (DDR5)
Pipelining No Yes (BIU/EU separation) Deep out-of-order execution (10+ stages)
Memory Management None Segmented (CS, DS, SS, ES) Paging + virtual memory (4KB pages)
Multitasking No Limited (real mode) Full (protected mode, SMP)
Power Efficiency High (no sleep modes) Moderate Ultra-low (ARM: 0.5W–5W; Intel: 65W–250W)

1.3 Why the Shift from 8085 to 8086?

The 8086 introduced three critical improvements over the 8085:

  1. 16-bit architecture: Doubled data width (16-bit registers like AX, BX) and address bus (20-bit for 1MB memory).
  2. Pipelined execution:
    • Bus Interface Unit (BIU): Fetches instructions from memory.
    • Execution Unit (EU): Executes instructions.
    • Example: While the EU executes ADD AX, BX, the BIU fetches the next instruction, hiding memory latency.
  3. Segmented memory model:
    • Divided memory into segments (code, data, stack, extra) using segment registers (CS, DS, SS, ES).
    • Real-world tie: eSewa’s payment gateway uses segmented memory to isolate transaction data (stack) from code (code segment).
0481215Instruction Format8 bits8 bitsAddress Bus8 bits8 bitsData Bus8 bits8 bitsPipeline8 bits8 bits
Key architectural differences between 8085 and 8086


2. Microprocessor vs. Microcontroller: Key Differences

Feature Microprocessor (e.g., 8086) Microcontroller (e.g., Arduino ATMega328)
Definition General-purpose CPU Integrated CPU + memory + peripherals
Memory External (RAM/ROM) On-chip (Flash, EEPROM, SRAM)
Peripherals External (UART, timers via chips) On-chip (ADC, PWM, UART, SPI)
Power Consumption Higher (PC CPUs: 65W–250W) Lower (Arduino: 50–200mA)
Use Case PCs, servers, embedded systems IoT, robotics, automotive (e.g., NTC’s smart meters)
Programming Assembly/C/C++ (complex OS) C/C++ (lightweight RTOS or bare metal)

2.1 Microprocessor-Based System Organization

A microprocessor requires supporting chips to form a functional system. The block diagram below shows the 8085-based system:

Real-world example:

  • Pathao’s ride-hailing app uses a microprocessor-based server (e.g., Intel Xeon) for:
    • Memory: Storing user data (RAM) and app code (ROM).
    • I/O: GPS modules (serial communication via UART), payment gateways (PCIe interface).
    • Peripherals: RAID arrays (for data redundancy), network cards (Ethernet).

3. Short Notes: Critical Components

3.1 Interrupts: Polled vs. Vectored

Type Polled Interrupts Vectored Interrupts
Definition CPU checks devices periodically for requests. Device sends interrupt signal + address.
Speed Slow (wastes CPU cycles) Fast (direct jump to ISR)
Example Checking if a printer is ready. Keyboard press triggering an ISR.
Use Case Simple systems (e.g., NTC’s old meters). Modern systems (e.g., WhatsApp’s message alerts).

Worked Example: Problem: Write an 8086 assembly program to handle a keyboard interrupt (IRQ1) using vectored interrupts. Solution:

; ISR for keyboard (IRQ1 = INT 0x09)
KEYBOARD_ISR:
    PUSHF           ; Save flags
    PUSH AX         ; Save registers
    IN AL, 0x60     ; Read scancode from keyboard port
    ; Process key (e.g., store in buffer)
    POP AX
    IRET            ; Return from interrupt

Real-world tie: Khalti’s payment OTP system uses vectored interrupts to instantly notify the server when a user enters an OTP, reducing latency.


3.2 Direct Memory Access (DMA)

Why DMA?

  • Problem: CPU must copy data (e.g., from a hard drive to RAM) byte-by-byte, wasting cycles.
  • Solution: DMA controller transfers data directly between peripherals and memory.

Block Diagram of 8237 DMA Controller:

Advantages:

  • Reduces CPU load (e.g., Daraz’s order processing streams product images via DMA to RAM).
  • Faster data transfer (e.g., Ncell’s 4G base stations use DMA for voice/data packets).

Disadvantages:

  • Complex hardware (requires DMA controller chip).
  • Risk of bus conflicts if not managed properly.

3.3 Universal Synchronous/Asynchronous Receiver Transmitter (USART/8251)

RS-232 vs. UART:

Feature RS-232 (Physical Layer) UART (Protocol)
Role Defines voltage levels (+/-12V). Defines start/stop bits, parity.
Speed Up to 20 kbps (limited by cable). Up to 1 Mbps (with short cables).
Use Case Legacy modems, serial ports. Modern GPS modules, Bluetooth.

8251 USART Architecture:

Real-world example:

  • NEPSE’s stock trading terminals use UART (via RS-232) to send real-time price updates to brokers’ screens.
  • WhatsApp’s backend uses USART for serial communication between load balancers and database servers.

3.4 Flag Registers in 8086

The 16-bit flag register in 8086 controls program flow. Key flags:

Flag Name Set When Example Use
CF Carry Flag Unsigned overflow (e.g., 80 + 90). Adjust ADD for unsigned arithmetic.
ZF Zero Flag Result is zero. Loop termination (JZ).
SF Sign Flag Result is negative. Check for negative numbers.
OF Overflow Flag Signed overflow (e.g., 127 + 1). Adjust ADD for signed arithmetic.
PF Parity Flag LSB has even parity. Error detection in serial comms.

Worked Example: Problem: Write an 8086 program to check if a number is positive/negative using flags. Solution:

MOV AL, [NUMBER]   ; Load number
TEST AL, AL        ; Set ZF/SF
JZ  IS_ZERO        ; Jump if zero
JS  IS_NEGATIVE    ; Jump if sign flag set (negative)
; Else, positive
JMP END_CHECK
IS_NEGATIVE:
    ; Handle negative case
JMP END_CHECK
IS_ZERO:
    ; Handle zero case
END_CHECK:

Real-world tie: Bank loan interest calculators (e.g., Nabil Bank’s software) use the SF flag to determine if a loan balance is negative (overdue) or positive.


4. In the Real World

  1. eSewa’s Payment Gateway:

    • Idea Used: Interrupts (vectored) and DMA.
    • How: When a user pays via eSewa, the server’s DMA controller streams transaction data to RAM without CPU intervention. Vectored interrupts instantly notify the payment processor to update the user’s balance.
  2. Pathao’s GPS Tracking:

    • Idea Used: USART (UART) and 8086’s segmented memory.
    • How: Pathao’s drivers’ phones send GPS coordinates via UART (serial port) to the backend server. The server uses segmented memory (like 8086’s DS/CS) to isolate driver data from ride data.
  3. NTC’s Smart Meters:

    • Idea Used: Microcontroller (ATMega328) vs. Microprocessor (8086).
    • How: Older meters used an 8085-based system with external memory, while newer meters use an ATMega328 microcontroller (on-chip memory, ADC for voltage sensing) to reduce power consumption.

5. Exam Tip

What Examiners Love to Test

  1. Comparisons:

    • Always draw tables (like the 8085 vs. 8086 or microprocessor vs. microcontroller).
    • Example: In 2022 PU exams, students lost marks by not comparing BIU/EU in 8086 with 8085’s unified architecture.
  2. Diagrams:

    • Mandatory for full marks:
      • Block diagrams of 8259 PIC, 8237 DMA, or 8251 USART.
      • Tip: Label every port and signal line (e.g., DREQ, DACK in DMA).
  3. Short Notes:

    • Polled vs. vectored interrupts: Explain with a real-world analogy (e.g., "Polled = calling a receptionist every 5 seconds; Vectored = receptionist calls you directly").
    • RS-232 vs. UART: Emphasize that RS-232 is physical (voltages); UART is logical (bits).
  4. Assembly Tricks:

    • For flag-related questions (e.g., "Check if a number is positive"), always show:
      • TEST/CMP instruction.
      • JZ/JS jumps.
      • Example: In 2021 PU exams, students scored full marks by writing a 3-line program using TEST AL, AL.
  5. Evolution Questions:

    • Memorize the timeline (8085 → 8086 → 80386 → Pentium → Core i7).
    • Key differences: Pipelining (8086), protected mode (80386), multi-core (Core Duo).
    • Tip: Relate modern CPUs to 8086’s BIU/EU split (e.g., "Modern CPUs use deeper pipelines like 8086’s BIU/EU but with 10+ stages").

Common Pitfalls

  • Forgetting to explain diagrams: Always write 2–3 sentences under each block diagram (e.g., "The 8259 PIC prioritizes interrupts using the IRR/ISR registers").
  • Mixing RS-232 and UART: RS-232 is a standard; UART is a protocol. Saying "RS-232 is UART" loses marks.
  • Ignoring real-world ties: Examiners reward 1–2 sentences linking concepts to apps (e.g., "DMA is used in Daraz’s image uploads to avoid CPU bottlenecks").

Final Checklist Before Exam: ✅ Can you draw all 3 block diagrams (8259, 8237, 8251) from memory? ✅ Do you know 5 differences between 8085 and 8086? ✅ Can you write a 3-line assembly program using flags? ✅ Have you linked 2 concepts to real-world apps (e.g., eSewa, Pathao)?

Based on the PU BE Computer (PU) syllabus for Microprocessor, unit 8.

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