Timing, Cycles & Instruction Execution in 8086

TAKEAWAYS:

• Clock cycles ≠ execution time: The 8086 uses T-states (clock pulses) to measure instruction duration, not raw clock speed.
• Bus cycles ≠ T-states: A single instruction may require multiple bus cycles (fetch, memory read/write, I/O), each with its own timing.
• Flags matter: Arithmetic/logic instructions modify flags (ZF, SF, CF, OF) that affect branching and loops.
• Real-world impact: CPU speed (MHz) directly affects timing—e.g., a 3 MHz 8085 takes 333 ns per T-state, while a 2 kHz 8086 takes 500 µs per T-state.
• Timing diagrams decode execution: Every instruction has a unique state diagram showing register/flag changes over cycles.
• DMA vs. CPU: Direct Memory Access (Unit 4) bypasses CPU timing for high-speed I/O (e.g., hard drives, network cards).

1. Clock and Timing Basics

The 8086’s system clock generates pulses (T-states) that synchronize all operations. Unlike modern CPUs, the 8086’s timing is not pipelined—each instruction executes sequentially.

Key Terms

Showing clock (CLK), address (AD0-AD15), and data (D0-D15) pins used in timing. (Image: lamfe, CC0, via Wikimedia Commons)

2. Timing Diagrams: How Instructions Execute

Every instruction has a timing diagram showing:

• T-states (clock pulses).
• Bus states (T1: fetch, T2-T4: memory/IO access).
• Signal changes (address, data, control lines like M/IO, RD, WR).

Example: ADD M (Add Memory to Accumulator)

stateDiagram-v2
    [*] --> T1: Fetch opcode (ADD)
    T1 --> T2: Fetch operand (M)
    T2 --> T3: Memory read (M → AL)
    T3 --> T4: AL ← AL + M
    T4 --> [*]: Flags updated (ZF, SF, CF, OF)

Worked Example (3 MHz Clock)

1. T1: Fetch ADD opcode (1 T-state).
2. T2-T4: Fetch operand (memory address) and execute (3 T-states).
3. Total: 4 T-states × 333 ns = 1.33 µs.

3. Bus Cycles in Detail

The 8086 uses 4 types of bus cycles for all operations:

Real-World Tie-In: eSewa Payment Processing When you pay via eSewa:

1. Your phone sends a memory write cycle to the bank’s server (storing transaction data).
2. The server responds with a memory read cycle (fetching your balance).
3. The 8086-like processor (or modern equivalent) handles these cycles in microseconds.

4. Instruction Execution: Step-by-Step Trace

Let’s trace LDA 2000H (Load Accumulator from memory address 2000H) at 2 kHz clock:

sequenceDiagram
    participant CPU
    participant Memory
    CPU->>Memory: T1: Fetch opcode (LDA)
    Memory-->>CPU: 0x2A (LDA opcode)
    CPU->>Memory: T2: Fetch operand (2000H)
    Memory-->>CPU: 2000H (address)
    CPU->>Memory: T3: Memory read (2000H → AL)
    Memory-->>CPU: Data at 2000H
    CPU-->>CPU: Update flags (ZF, SF)

Timing Calculation (2 kHz = 500 µs per T-state)

• T1: Fetch opcode (1 T-state).
• T2: Fetch operand (1 T-state).
• T3: Memory read (1 T-state).
• Total: 3 T-states × 500 µs = 1.5 ms.

Why This Matters for Exams

• Low clock speed (2 kHz) makes the 8086 slow by today’s standards (modern CPUs: GHz range).
• Memory access is the bottleneck: Even simple instructions take milliseconds at 2 kHz.

5. Flags and Their Impact on Timing

The 8086 has 6 flags in the FLAGS register, affected by arithmetic/logic instructions:

Worked Example: ADD AL,99 at 3 MHz

stateDiagram-v2
    [*] --> T1: Fetch ADD opcode
    T1 --> T2: Fetch 99
    T2 --> T3: AL ← AL + 99 (result = 100 if AL=1)
    T3 --> [*]: CF=1 (carry), ZF=0, SF=0, OF=0

Flags After Execution:

• CF=1 (carry occurred: 1 + 99 = 100).
• ZF=0 (result ≠ 0).
• SF=0 (result positive).
• OF=0 (no signed overflow).

Real-World Tie-In: Bank Loan Interest Calculation Banks use flag checks to validate transactions:

• If ADD sets CF=1, it triggers an overflow error (e.g., insufficient funds).
• Example: MOV AX,balance; ADD AX,deposit; JNC valid (jump if no carry).

6. Comparing 8085 vs. 8086 Timing

Why the 8086 is Faster (Despite Lower Clock)

• 16-bit architecture: Fetches 2 bytes per cycle (vs. 8085’s 1 byte).
• Pipelined execution: Overlaps fetch/decode/execute (partially).

7. Real-World Applications of Timing

1. Ncell’s Network Traffic Routing

• Problem: Ncell’s routers must prioritize data packets (like voice calls vs. emails).
• Solution: The router’s CPU (or microcontroller) uses timing diagrams to:
  • Allocate T-states for critical packets (voice: low latency).
  • Delay non-critical packets (emails: higher latency allowed).
• Example: A MOV instruction to update a packet’s priority queue takes 4 T-states at 5 MHz = 800 ns.

2. Daraz’s Order Processing System

• Problem: Daraz’s servers must process thousands of orders per second.
• Solution: The backend uses DMA (Direct Memory Access) to:
  • Bypass CPU timing for bulk data transfers (e.g., reading order lists from disk).
  • Free up the CPU for other tasks (e.g., updating inventory flags).
• Example: A STA instruction to store an order status takes 1 T-state (200 ns), but DMA transfers 1000 bytes in parallel without CPU intervention.

3. ATMs (Nabil Bank, Global IME)

• Problem: ATMs must respond within 2 seconds to user inputs.
• Solution: The ATM’s microcontroller (8086-like) uses:
  • Interrupt-driven timing: A keypress triggers an interrupt, and the CPU executes a 4-T-state IN instruction to read the port.
  • Flag checks: After ADD (e.g., balance + withdrawal), it checks CF to deny overdrafts.

8. Exam Tip: How to Score Full Marks

Do’s:

✅ Draw timing diagrams with labels:

• Show T-states, bus cycles, and signal changes (e.g., AD0-AD15, RD, WR).
• Example: For LDA 2000H, label T1 (fetch opcode), T2 (fetch address), T3 (memory read).

✅ Calculate execution time correctly:

• Formula: Total T-states × (1/clock speed).
• Example: ADD M at 3 MHz = 4 T-states × 333 ns = 1.33 µs.

✅ Explain flags with examples:

• Always show before/after flag states for arithmetic/logic instructions.
• Example: SUB AL,BL → CF=1 if borrow occurs.

✅ Compare 8085 vs. 8086:

• Highlight data bus width, addressing, and flag differences.

Don’ts:

❌ Assume clock speed is execution speed:

• 3 MHz ≠ 3 instructions/µs! Always convert to T-states.

❌ Forget bus cycles:

• Even simple instructions like MOV require fetch + memory cycles.

❌ Ignore flags in ALP questions:

• Always check how JZ, JC, JO use flags (e.g., JC overdraft_error).

9. Practice Questions (Exam-Style)

a) Draw and explain the timing diagram for STA 3000H at 5 MHz.

Answer:

stateDiagram-v2
    [*] --> T1: Fetch STA opcode
    T1 --> T2: Fetch 3000H (address)
    T2 --> T3: Memory write (AL → 3000H)
    T3 --> [*]: Instruction complete

Execution Time: 3 T-states × 200 ns = 600 ns.

b) Write an ALP to check if two numbers in memory are equal (use flags).

MVI C,00H       ; Clear carry flag (not needed here, but good practice)
MOV AL,[NUM1]   ; Load first number
CMP AL,[NUM2]   ; Compare with second number
JZ EQUAL        ; Jump if ZF=1 (numbers equal)
JNZ NOT_EQUAL   ; Else, jump
EQUAL: MOV BL,01H ; Set BL=1 if equal
JMP END
NOT_EQUAL: MOV BL,00H ; Set BL=0 if not equal
END: HLT

c) Why does ADD AX,BX take longer than ADD AL,BL?

• 16-bit vs. 8-bit:
  • ADD AL,BL: 3 T-states (8-bit).
  • ADD AX,BX: 3 T-states (fetch) + 3 T-states (execute) + 3 T-states (flags) = 9 T-states.
• Flag updates: 16-bit ADD must check OF (overflow flag), adding cycles.

10. Summary Table: Key Instructions and Timing