Interrupts & DMA: 8085/8086 Controllers, DMA Transfers & I/O Methods

TAKEAWAYS:

• Interrupts free the CPU from polling by triggering on events (e.g., keyboard press, timer expiry), handled via 8259A PIC (Programmable Interrupt Controller) with priority levels and masking.
• DMA (Direct Memory Access) bypasses the CPU for high-speed data transfers (e.g., hard drives, network cards) using 8257 DMA controller, reducing CPU load.
• Memory-mapped I/O uses memory addresses for I/O devices (simpler), while I/O-mapped I/O uses dedicated IN/OUT instructions (faster for simple devices).
• Vectored interrupts automatically jump to service routines via interrupt vectors, while polled interrupts require manual checking.
• DMA modes (single, burst, demand) optimize data transfer speed for real-time applications like Khalti payments or NTC network traffic.
• Exam focus: Block diagrams (8259A, DMA controller), comparisons (polled vs. vectored), and worked examples (e.g., calculating DMA transfer time).

1. Interrupts: Definition, Types, and 8259A PIC

What is an Interrupt?

An interrupt is a signal sent to the CPU by hardware/software to request immediate attention. It suspends the current program, executes an Interrupt Service Routine (ISR), then resumes. Without interrupts, the CPU would waste time polling devices (checking repeatedly if they need service).

Types of Interrupts

mindmap
  root((Interrupts))
    Hardware
      Keyboard press
      Timer expiry
      External signals
    Software
      Programmed (INT n)
      Trap (Debugging)
    Maskable
      Can be ignored (e.g., INTR)
    Non-Maskable (NMI)
      Critical (e.g., power failure)

Interrupt Sources in 8085/8086

8259A Programmable Interrupt Controller (PIC)

The 8259A manages 8 maskable interrupts (IRQ0–IRQ7) in 8085/8086 systems. It:

1. Prioritizes interrupts (e.g., keyboard > timer).
2. Masks interrupts (ignores them if needed).
3. Generates interrupt vectors (addresses for ISRs).

Key Registers of 8259A:

• ICW1–ICW4: Initialization Command Words (set mode, cascading, vector base).
• OCW1: Mask register (disable/enable IRQs).
• OCW2: Read IRR (Interrupt Request Register) or ISR (In-Service Register).

Interrupt Handling Steps (8085/8086)

1. CPU finishes current instruction.
2. Saves PSW (Program Status Word) and PC (Program Counter) on the stack.
3. Sends INTA (Interrupt Acknowledge) to 8259A.
4. 8259A sends interrupt vector (address of ISR).
5. CPU jumps to ISR, executes, then IRET (return from interrupt).

2. Polled vs. Vectored Interrupts

Worked Example: Bank Transaction Interrupt (8085)

• Scenario: An ATM (using 8085-based system) processes transactions.
• Problem: Without interrupts, the CPU must poll the card reader every 10ms.
• Solution: Use INTR (IRQ) from the card reader.
  • When a card is inserted, the reader sends INTR.
  • 8259A sends vector 00030H (predefined for IRQ2).
  • CPU jumps to ISR at 00030H, reads card data, and processes payment.
• Time Saved: Polling wastes 99% of CPU time; interrupts use <1%.

3. Direct Memory Access (DMA)

Why DMA?

The CPU is too slow for high-speed devices like:

• Hard drives (100MB/s).
• Network cards (1Gbps).
• Sound cards (44.1kHz audio).

DMA solves this by transferring data directly between memory and I/O devices, bypassing the CPU.

DMA Controller (8257)

The 8257 manages DMA transfers with:

1. Request (HRQ): Device (e.g., disk) asks for DMA.
2. Acknowledge (HLDA): CPU grants DMA.
3. Data Transfer: Device ↔ Memory via DMA bus.
4. Completion: DMA controller signals CPU.

sequenceDiagram
    participant CPU
    participant DMA8257
    participant HardDrive
    CPU->>DMA8257: HLDA (Grant)
    HardDrive->>DMA8257: HRQ (Request)
    DMA8257->>HardDrive: Data Transfer (Burst Mode)
    DMA8257->>CPU: EOP (End of Process)
    CPU->>DMA8257: Reset

Key Registers of 8257:

• Mode Set Register: Single, burst, or demand transfer.
• Request Register: Device requests DMA.
• Mask Register: Enable/disable DMA channels.
• Status Register: Transfer complete/error flags.

DMA Transfer Modes

Worked Example: eSewa Payment DMA Transfer

• Scenario: A user pays ₹1000 via eSewa (simulated on 8086).
• Problem: Sending payment data to the bank’s server requires fast transfer.
• Solution: Use DMA (8257) in burst mode.
  • Payment data (1KB) is transferred in 3 bursts (each 512 bytes).
  • Time per burst: 10μs (vs. 1ms with CPU polling).
  • Total time: 30μs (vs. 1ms → 33x faster).

4. Memory-Mapped I/O vs. I/O-Mapped I/O

Worked Example: Ncell SIM Card Reader (I/O-Mapped)

• Scenario: An 8085-based SIM card reader reads phone numbers.
• Method: Uses I/O-mapped I/O (port 01H).

  IN AL, 01H   ; Read from SIM card port
  MOV [2000H], AL ; Store in memory
  

• Advantage: Faster than memory-mapped for small data transfers.

5. Interrupts and DMA in Real-World Systems

In the Real World

1. eSewa/Khalti (Nepal)

   • Interrupts: When a user taps "Pay," the mobile app sends an interrupt to the server to process the transaction (like 8085’s INTR).
   • DMA: High-speed payment data (e.g., ₹5000) is transferred via DMA-like mechanisms in modern servers to avoid CPU bottlenecks.

2. Ncell Network Traffic

   • Interrupts: Base stations send interrupts to the core network when a call is received (prioritizing emergency calls).
   • DMA: Data packets (e.g., WhatsApp messages) use DMA controllers in routers to forward traffic without CPU delays.

3. Bank Loan Interest Calculation (8085 Simulation)

   • Scenario: A bank’s legacy system (8085-based) calculates monthly interest.
   • Problem: Polling the interest table wastes CPU time.
   • Solution: Use vectored interrupts when new loan data arrives.

     ; ISR for loan data interrupt (IRQ1)
     ORG 00038H
     INTERRUPT_SERVICE:
         IN AL, 02H   ; Read loan amount from port
         CALL CALC_INTEREST
         IRET
     

6. Exam Tip: What to Focus On

1. Block Diagrams (Full Marks)

   • Draw 8259A PIC with all pins (ICW1–OCW3, IRQ0–IRQ7).
   • Draw 8257 DMA controller with HRQ/HLDA, channels, and registers.
   • Example Question: "Draw and explain the block diagram of 8259A." → Must include:
     • Data bus, address bus, control lines.
     • IRR, ISR, IMR registers.
     • Cascading (if applicable).

2. Worked Examples (2–3 Marks)

   • Interrupts: Calculate ISR address given a vector (e.g., RST 6.5 → 00034H).
   • DMA: Calculate transfer time (e.g., 1KB in burst mode at 10MB/s → 100μs).
   • I/O: Write assembly for memory-mapped vs. I/O-mapped access.

3. Comparisons (1–2 Marks)

   • Polled vs. Vectored: Explain why vectored is faster.
   • Memory-mapped vs. I/O-mapped: When to use each.

4. Short Notes (5 Marks)

   • Polled vs. Vectored Interrupt: Define and compare.
   • DMA Modes: List and explain single/burst/demand.
   • 8259A vs. 8257: PIC vs. DMA controller roles.