Memory Mapping, I/O Interfacing, and Address Decoding in 8085

Memory and I/O Interfacing in 8085

1. Memory Mapping vs. I/O Mapped I/O

The 8085 microprocessor can interface with Input/Output (I/O) devices in two distinct ways: I/O Mapped I/O and Memory Mapped I/O. Understanding the difference is critical for exam questions asking for definitions and distinctions.

I/O Mapped I/O

In this scheme, I/O devices are assigned unique addresses within a separate 64KB I/O space (0000H to FFFFH). The 8085 has dedicated instructions for I/O operations: IN and OUT. The IO/M pin is asserted low (0) during I/O operations.

• Address Space: 64KB (0000H – FFFFH).
• Instructions: IN port, OUT port, data.
• Control Signal: IO/M = 0.
• Advantage: Does not consume memory space; simpler hardware for small systems.
• Disadvantage: Limited to 64KB I/O space; fewer instructions available for I/O (only IN/OUT).

Memory Mapped I/O

In this scheme, I/O devices are treated as memory locations. They are assigned addresses within the 64KB memory space. The 8085 uses standard memory instructions (LDA, STA, MOV) to access I/O devices. The IO/M pin is asserted high (1) during memory operations, but since I/O is mapped to memory, the hardware logic treats these specific memory addresses as I/O devices.

• Address Space: Part of the 64KB memory space.
• Instructions: LDA addr, STA addr, data.
• Control Signal: IO/M = 1 (logically, though the device responds to memory signals).
• Advantage: All memory instructions can be used for I/O; easier to program with complex data operations.
• Disadvantage: Consumes memory space; slightly slower due to memory cycle overhead.

flowchart TD
    A["8085 Microprocessor"] --> B{"IO/M Pin State"}
    B -->|"0"| C["I/O Mapped I/O"]
    B -->|"1"| D["Memory Mapped I/O"]
    C --> E["Uses IN/OUT Instructions"]
    C --> F["64KB I/O Space"]
    D --> G["Uses LDA/STA Instructions"]
    D --> H["Shares 64KB Memory Space"]

2. Address Decoding

When interfacing multiple memory chips (RAM/ROM) or I/O devices, the 8085 must select the correct chip based on the address on the address bus. This is done using Address Decoding.

The 8085 has 16 address lines ($A_{15}$ to $A_0$). To select a specific memory chip, we use a decoder IC, such as the 74LS138 (3-to-8 line decoder).

How 74LS138 Works

The 74LS138 has 3 address inputs ($C,B,A$), 3 enable inputs ($\overline{G_1},\overline{G_{2A}},\overline{G_{2B}}$), and 8 outputs ($Y_0$ to $Y_7$). Only one output is active low at a time, corresponding to the binary value on the inputs.

Example: Suppose we want to select a RAM chip when the address is in the range 2000H to 27FFH.

• Binary of 2000H: 0010 0000 0000 0000
• Binary of 27FFH: 0010 0111 1111 1111

The upper 5 bits (00100) are constant for this range. We can use these bits to enable the decoder.

• $A_{15}=0$
• $A_{14}=0$
• $A_{13}=1$
• $A_{12}=0$
• $A_{11}=0$

We connect $A_{13}$ to $G_1$ (active high), and $\overline{A_{15}}$, $\overline{A_{14}}$, $\overline{A_{12}}$, $\overline{A_{11}}$ to the enable inputs (active low). The output $Y_0$ will be active low when the address is in the 2000H to 2FFFH range. This output is connected to the Chip Select ($\overline{CS}$) pin of the RAM.

flowchart LR
    A["Address Bus A15-A0"] --> B["74LS138 Decoder"]
    B --> C["Y0: Selects RAM 1"]
    B --> D["Y1: Selects ROM 1"]
    B --> E["Y2: Selects I/O Port"]
    C --> F["RAM Chip"]
    D --> G["ROM Chip"]
    E --> H["I/O Device"]

3. Interfacing RAM and ROM

Calculating Number of Chips

To interface a memory block, we first calculate the number of chips required.

Formula: $$\text{Number of Chips}=\frac{\text{Total Memory Size}}{\text{Chip Size}}$$

Example: Interface 2KB RAM and 4KB ROM.

• RAM Chip Size: 1KB (8K x 8 bits).

• ROM Chip Size: 4KB (32K x 8 bits).

• RAM: $2\text{KB}/1\text{KB}=2$ chips.

• ROM: $4\text{KB}/4\text{KB}=1$ chip.

Address Range Allocation

We must assign non-overlapping address ranges to each chip.

• RAM 1: 2000H to 27FFH (2KB)
• RAM 2: 2800H to 2FFFH (2KB)
• ROM 1: 3000H to 3FFFH (4KB)

Circuit Diagram

The circuit connects the 8085 address bus to the decoder inputs. The decoder outputs connect to the $\overline{CS}$ pins of the memory chips. The data bus ($D_7$ to $D_0$) connects to the data pins of all chips (tri-state buffers are used if necessary, but 8085 memory chips usually have tri-state outputs). The control signals $RD$ and $WR$ connect to the read/write pins of the chips.

4. I/O Interfacing

I/O Mapped I/O Circuit

For I/O mapped I/O, the I/O device is selected using the lower 8 address lines ($A_7$ to $A_0$) and the IO/M signal. The IO/M signal is used to enable the I/O decoder.

Example: Interface an 8-bit input port at address 00H and an 8-bit output port at address 01H.

• Input Port: Enabled when IO/M = 0 and $A_7$ to $A_0$ = 0000 0000.
• Output Port: Enabled when IO/M = 0 and $A_7$ to $A_0$ = 0000 0001.

A 2-to-4 line decoder (74LS139) can be used. The IO/M signal is connected to the enable pin. The address lines $A_0$ and $A_1$ are connected to the decoder inputs.

sequenceDiagram
    participant CPU as 8085 CPU
    participant Decoder as I/O Decoder
    participant Port as I/O Port
    CPU->>Decoder: Address 00H, IO/M=0
    Decoder->>Port: Chip Select Active
    CPU->>Port: IN Instruction
    Port-->>CPU: Data

Memory Mapped I/O Circuit

For memory mapped I/O, the I/O device is selected using the full 16-bit address bus, just like memory. The IO/M signal is high (1), but the decoder logic is designed to select the I/O device for specific memory addresses.

Example: Interface an 8-bit input port at memory address 4000H.

• Address: 4000H = 0100 0000 0000 0000.
• Decoder: Use 74LS138 with $A_{15}$ to $A_{13}$ as inputs.
• Selection: When address is 4000H to 47FFH, the decoder output is active, selecting the I/O port.

5. Worked Example: Interfacing 2KB RAM

Problem: Interface 2KB RAM starting at address 2000H using 1KB RAM chips.

Step 1: Calculate Chips $$\text{Chips}=\frac{2\text{KB}}{1\text{KB}}=2\text{ chips}$$

Step 2: Assign Addresses

• RAM 1: 2000H to 27FFH
• RAM 2: 2800H to 2FFFH

Step 3: Decoder Logic We need to select RAM 1 when the address is in 2000H to 27FFH.

• Binary 2000H: 0010 0000 0000 0000
• Binary 27FFH: 0010 0111 1111 1111

The upper 5 bits are 00100.

• $A_{15}=0$
• $A_{14}=0$
• $A_{13}=1$
• $A_{12}=0$
• $A_{11}=0$

Connect $A_{13}$ to $G_1$ of 74LS138. Connect $\overline{A_{15}}$, $\overline{A_{14}}$, $\overline{A_{12}}$, $\overline{A_{11}}$ to $\overline{G_{2A}}$ and $\overline{G_{2B}}$ (using AND gates if necessary). The output $Y_0$ selects RAM 1.

For RAM 2 (2800H to 2FFFH):

• Binary 2800H: 0010 1000 0000 0000
• Binary 2FFFH: 0010 1111 1111 1111

The upper 5 bits are 00101.

• $A_{15}=0$
• $A_{14}=0$
• $A_{13}=1$
• $A_{12}=0$
• $A_{11}=1$

Connect $A_{13}$ and $A_{11}$ to $G_1$ (using AND gate). Connect $\overline{A_{15}}$, $\overline{A_{14}}$, $\overline{A_{12}}$ to enable inputs. The output $Y_1$ selects RAM 2.

6. Comparison Table

7. In the real world

• eSewa and Khalti Payment Gateways: These applications use Memory Mapped I/O to communicate with secure hardware modules (HSMs) that process payment transactions. The HSM is assigned a specific memory address, and the microcontroller uses standard memory read/write instructions to send transaction data to the HSM for encryption. This allows the use of complex data manipulation instructions directly on the payment data before it is sent to the hardware.
• NTC and Ncell Base Stations: The base station controllers use I/O Mapped I/O for real-time control signals, such as switching antennas or adjusting power levels. These operations require fast, dedicated I/O instructions (IN/OUT) to ensure low latency in communication with the radio hardware. The separate I/O space allows the processor to quickly poll status registers without interfering with the main memory used for voice data buffering.
• Daraz Order Processing Servers: The server microprocessors use Address Decoding to manage large amounts of RAM. The 74LS138 decoder logic is implemented in the memory controller to select specific RAM banks. When the CPU accesses an address in the 2000H to 2FFFH range, the decoder activates the chip select for the RAM bank containing the current order queue data. This ensures that the correct data is retrieved for processing the user's order.

8. Exam tip

• Draw the Circuit: Always draw the complete circuit diagram for interfacing questions, including the 8085, decoder, and memory/I/O chips. Label all address lines, data lines, and control signals.
• Show Decoder Logic: Explicitly show how the address bits are connected to the decoder inputs and enable pins. Write down the binary address range and identify the constant bits.
• Compare Clearly: For questions asking to differentiate between I/O mapped and memory mapped I/O, use a table format to clearly list the differences in address space, instructions, and control signals.
• Calculate Chips: Always show the calculation for the number of chips required. State the chip size and total memory size clearly.
• Use Standard Symbols: Use standard logic gate symbols (AND, OR, NOT) and decoder symbols in your diagrams. Ensure that active low signals are marked with a bar or bubble.