Computer Architecture Basics: Definitions, Components & Functional Views

TAKEAWAYS:

• Computer architecture defines the visible structure (ISA, instruction formats) while organization describes the invisible implementation (circuitry, wiring).
• The IAS architecture (1946) introduced the stored-program concept, separating memory, CPU, and I/O—still the basis for modern computers.
• A CPU’s functional view includes the control unit (fetches/decodes instructions), ALU (performs arithmetic/logic), and registers (fast temporary storage).
• Instruction formats (e.g., 0-address, 1-address) dictate how many operands an instruction carries, affecting efficiency (e.g., stack vs. accumulator architectures).
• Addressing modes (e.g., immediate, indirect, indexed) determine how operands are specified, impacting code size and performance.
• Registers (PC, IR, MAR, MBR, ACC) act as the CPU’s "scratchpad," enabling fast operations but limited in number.

1. Definitions: Architecture vs. Organization

Computer architecture and organization are often confused, but they refer to different levels of abstraction:

classDiagram
    class Architecture {
        +Visible to programmer
        +Instruction Set Architecture (ISA)
        +Instruction formats
        +Addressing modes
        +Memory addressing
    }
    class Organization {
        +Invisible to programmer
        +Hardware implementation
        +Register transfer language (RTL)
        +Control unit design
        +Data paths
    }
    Architecture -->|"Defines"| Organization : "What" to "How"

Key Difference:

Why it matters:

• A programmer sees only the architecture (e.g., x86 vs. ARM ISA).
• The organization determines speed, power, and cost (e.g., Intel’s Core i7 vs. Apple’s M1 chip).

2. The IAS Computer Architecture (1946)

The Institute for Advanced Study (IAS) computer, designed by John von Neumann, introduced the stored-program concept, which is the foundation of modern computers. Its architecture included:

Key Features:

1. Binary arithmetic: Used for both data and instructions (stored-program concept).
2. Memory: 64 words of 40 bits each (1 word = 1 instruction or data).
3. Registers:
   • Accumulator (AC): Holds operands and results.
   • Multiplier-Quotient (MQ): Used for multiplication/division.
   • Instruction Register (IR): Holds the current instruction.
   • Program Counter (PC): Points to the next instruction.
4. I/O: Used punch cards and paper tape (slow by today’s standards).

Real-World Connection:

• Modern CPUs still use the von Neumann architecture, but with caches, pipelining, and multicore designs.
• Example: Your smartphone’s ARM Cortex processor follows this basic structure but with billions of transistors and multi-level caches.

3. Functional View of a Computer

A computer’s operation can be broken down into five functional units, working together in a cycle:

stateDiagram-v2
    [*] --> Fetch
    Fetch --> Decode
    Decode --> Execute
    Execute --> Memory
    Memory --> I/O
    I/O --> [*]

Components:

1. Input Unit: Receives data (keyboard, mouse, sensors).
2. Memory Unit: Stores data and instructions (RAM, ROM).
3. Arithmetic Logic Unit (ALU): Performs calculations and logic operations.
4. Control Unit (CU): Manages instruction execution (fetch-decode-execute cycle).
5. Output Unit: Displays results (monitor, printer, speakers).

How It Works:

1. Fetch: The CU fetches an instruction from memory using the Program Counter (PC).
2. Decode: The instruction is decoded to determine the operation.
3. Execute: The ALU performs the operation (e.g., addition, comparison).
4. Memory Access: Data is read from/written to memory if needed.
5. Output: Results are sent to the output unit.

Worked Example: Adding Two Numbers Assume we want to compute X = A + B:

1. Fetch: PC points to LOAD A, instruction is fetched into IR.
2. Decode: CU decodes LOAD A and sends signals to load A into the Accumulator (AC).
3. Execute: A is loaded into AC.
4. Fetch: Next instruction (ADD B) is fetched.
5. Decode/Execute: B is added to AC.
6. Store: Result (X) is stored in memory.

4. Registers: The CPU’s Fast Storage

Registers are small, ultra-fast storage locations inside the CPU, used to hold data temporarily. They are limited in number (typically 16–64 in modern CPUs) but much faster than memory.

classDiagram
    class Register {
        +Size: 8-bit to 64-bit
        +Access time: ~1 clock cycle
        +Used for: Temporary storage, instruction pointers, operands
    }
    Register <|-- PC : "Program Counter"
    Register <|-- IR : "Instruction Register"
    Register <|-- MAR : "Memory Address Register"
    Register <|-- MBR : "Memory Buffer Register"
    Register <|-- ACC : "Accumulator"
    Register <|-- SP : "Stack Pointer"

Common Registers and Their Uses:

Why Registers Matter:

• Speed: Accessing a register takes ~1 clock cycle, while accessing RAM takes ~100 cycles.
• Efficiency: Reduces memory access, speeding up programs.
• Limitation: Only a few registers exist, so programmers must manage them carefully.

Real-World Example: Pathao’s Ride Allocation When you request a ride on Pathao, the app:

1. Uses the PC to fetch the next instruction (e.g., "Check nearest driver").
2. The ACC holds the driver’s location data temporarily.
3. The SP manages the stack for recursive functions (e.g., pathfinding algorithms).

5. Instruction Formats and Addressing Modes

A. Instruction Formats

Instructions consist of opcode (operation) and operand(s). The format depends on the addressing mode and ISA.

Comparison of Instruction Formats:

Worked Example: Evaluating X = (M*N) + (P*Q) Using 3-address instructions:

1. MUL T1, M, N (T1 = M * N)
2. MUL T2, P, Q (T2 = P * Q)
3. ADD X, T1, T2 (X = T1 + T2)

Using 1-address (accumulator):

1. LOAD M
2. MUL N
3. STORE T1
4. LOAD P
5. MUL Q
6. ADD T1
7. STORE X

Why It Matters:

• RISC (Reduced Instruction Set Computing) uses 2-address for simplicity.
• CISC (Complex Instruction Set Computing) uses 3-address for complex operations in fewer instructions.

B. Addressing Modes

Addressing modes determine how operands are specified in an instruction. They affect code size, speed, and flexibility.

classDiagram
    class AddressingMode {
        +Immediate: Operand is part of instruction
        +Direct: Operand is memory address
        +Indirect: Operand is address of address
        +Register: Operand is in a register
        +Register Indirect: Operand is at address in register
        +Indexed: Operand = base + index
        +Relative: Operand = PC + offset
    }

Common Addressing Modes with Examples:

Worked Example: Array Traversal in C

for (int i = 0; i < 10; i++) {
    sum += array[i];  // Indexed addressing: array + i
}

• Assembly (x86): MOV EAX, [ARRAY + EBX] (where EBX holds i).
• Why? Indexed addressing avoids recalculating array + i every time.

Real-World Example: Daraz’s Order Processing When you place an order on Daraz:

1. The indexed addressing mode is used to access your cart items in memory.
   • LOAD [CART + INDEX] (where INDEX is your item number).
2. The immediate mode loads constants like TOTAL_ITEMS = 5.
3. The relative mode handles jumps to different order-processing functions.

6. Bus and Register Transfers

A. Buses: The Data Highway

Buses are shared communication pathways that transfer data between components. There are three main types:

Bus Characteristics:

Worked Example: Loading Data from Memory

1. Address Bus: CPU sends 0x1000 (memory address) to RAM.
2. Control Bus: CPU sends READ signal.
3. Data Bus: RAM sends data at 0x1000 back to CPU.

B. Register Transfers

Register transfers move data between registers and memory using buses. They are described in Register Transfer Language (RTL).

Example RTL Operations:

Worked Example: ADD R1, R2 in RTL

1. (MAR) ← (PC) (Load PC into MAR)
2. (MDR) ← (M[MAR]) (Fetch instruction from memory)
3. (IR) ← (MDR) (Load instruction into IR)
4. (AC) ← (AC) + (R2) (Add R2 to AC)
5. (PC) ← (PC) + 1 (Increment PC)

7. Computer Classification and Flynn’s Taxonomy

Computers are classified based on instruction and data streams. Flynn’s Taxonomy categorizes them into four types:

classDiagram
    class Computer {
        +SISD: Single Instruction, Single Data
        +SIMD: Single Instruction, Multiple Data
        +MISD: Multiple Instruction, Single Data (rare)
        +MIMD: Multiple Instruction, Multiple Data
    }

Comparison Table:

Real-World Examples:

1. SISD: Your laptop’s Intel Core i5 (single-core mode).
2. SIMD: NVIDIA GPUs (used in gaming and AI training).
3. MIMD: Google’s data centers (thousands of servers working in parallel).

In the Real World

1. eSewa’s Payment Processing

   • Uses SIMD in its servers to process thousands of transactions per second (e.g., ADD balance, amount applied to multiple accounts simultaneously).
   • Registers hold temporary transaction data (e.g., ACC stores the new balance).
   • Indexed addressing accesses user accounts in a database (e.g., LOAD [USERS + ID]).

2. Khalti’s Loan Interest Calculation

   • When calculating monthly installments, Khalti’s backend uses:
     • 3-address instructions for clarity (e.g., MUL principal, rate, time).
     • Pipelining (Unit 7) to speed up calculations for millions of users.
   • Cache memory (Unit 6) stores frequently accessed loan terms.

3. NTC’s Traffic Route Optimization

   • NTC’s traffic management system uses MIMD (multiple sensors, multiple instructions) to:
     • SIMD: Process traffic data from all cameras simultaneously (e.g., ADD speed1, speed2, ...).
     • Indexed addressing: Access route data (e.g., LOAD [ROUTES + CAMERA_ID]).
   • Registers hold real-time traffic counts (e.g., ACC stores total vehicles on a road).

Exam Tip

1. Definitions First:

   • Always define architecture (logical) vs. organization (physical) clearly.
   • For IAS architecture, mention binary arithmetic, stored-program concept, and registers (AC, MQ, IR, PC).

2. Diagrams Are Mandatory:

   • Draw the IAS architecture block diagram (memory, CPU, I/O).
   • Show instruction formats (0-, 1-, 2-, 3-address) with examples.
   • Illustrate addressing modes with memory diagrams (e.g., indirect vs. indexed).

3. Worked Examples:

   • For addressing modes, show how array[i] is accessed using indexed addressing.
   • For instruction formats, compare 3-address vs. 1-address for the same operation (e.g., X = A + B).

4. Real-World Links:

   • Connect registers to app performance (e.g., "Why does Pathao need fast registers?").
   • Relate Flynn’s Taxonomy to Nepali tech (e.g., "How does Ncell’s 5G use SIMD?").

5. Common Pitfalls:

   • Don’t confuse:
     • Addressing modes (how operands are specified) vs. instruction formats (how many operands).
     • Bus types (data, address, control) vs. register transfers (RTL operations).
   • Avoid vague answers: Always give examples (e.g., "Indexed addressing is used in for loops").

6. Past Exam Patterns:

   • Part (a): Define and explain (e.g., "Differentiate architecture and organization").
   • Part (b): Compare or apply (e.g., "Evaluate X = (M*N) + (P*Q) using 3-address instructions").
   • Diagrams: Always include block diagrams for architectures and memory diagrams for addressing modes.

Block diagram of the IAS computer showing memory, CPU, and I/O units (Image: Kapooht, CC BY-SA 3.0, via Wikimedia Commons)