Solid State Physics & Semiconductors: Band Theory, Doping, ICs & Devices

1. Crystal Structure and Bonding in Solids

Key Concepts

• Crystal Lattice: Atoms/molecules arranged in a repeating 3D pattern (unit cell).
• Types of Bonding:
  • Metallic: Free electrons (delocalized) → high conductivity (e.g., copper).
  • Ionic: Strong electrostatic bonds (e.g., NaCl) → brittle, high melting point.
  • Covalent: Shared electrons (e.g., diamond, silicon) → directional, strong.
  • Van der Waals: Weak intermolecular forces (e.g., graphite layers).

Real-World Example: Silicon in Electronics

Silicon (Si) has a diamond cubic structure (covalent bonds), making it ideal for semiconductors. Its 4 valence electrons form stable bonds, but thermal energy can excite electrons to the conduction band → basis for all modern chips.

graph LR
    A["Crystal Structure"] --> B["Unit Cell"]
    B --> C["Bravais Lattice"]
    C --> D["Simple Cubic"]
    C --> E["Body-Centered Cubic"]
    C --> F["Face-Centered Cubic"]
    C --> G["Hexagonal Close-Packed"]
    G --> H["Silicon: Diamond Cubic"]

2. Band Theory of Solids

Energy Bands and Classification

• Valence Band (VB): Filled with electrons at 0 K.
• Conduction Band (CB): Empty at 0 K; electrons here can move freely.
• Band Gap (Eg): Energy difference between VB and CB.
  • Intrinsic Semiconductors: Pure Si/Ge (Eg ~1 eV). Conductivity increases with temperature (more electron-hole pairs).
  • Extrinsic Semiconductors: Doped with impurities (e.g., P in Si → n-type; B in Si → p-type).

Worked Example: Silicon’s Band Gap

At room temperature (300 K), the intrinsic carrier concentration $n_i$ for Si is $1.5\times 10^{10}{\text{cm}}^{-3}$. Calculate the band gap $E_g$ using: $$n_i=\sqrt{N_c{N}_v}\exp \left(-\frac{E_g}{2kT}\right)$$ Where:

• $N_c,N_v$: Effective density of states (~$10^{19}{\text{cm}}^{-3}$).
• $k$: Boltzmann constant ($8.62\times 10^{-5}\text{eV/K}$).
• $T=300\text{K}$.

Solution: $$E_g=2kT\ln \left(\frac{\sqrt{N_c{N}_v}}{n_i}\right)=1.1\text{eV}$$

3. Doping and Semiconductor Types

Doping Process

• n-type: Add pentavalent impurities (e.g., P, As) → extra electron → majority carriers = electrons.
• p-type: Add trivalent impurities (e.g., B, Al) → "hole" (missing electron) → majority carriers = holes.

Carrier Concentration

For an n-type semiconductor: $$n_0=N_d(\text{if fully ionized})$$ For a p-type semiconductor: $$p_0=N_a(\text{if fully ionized})$$ Where $N_d$ = donor concentration, $N_a$ = acceptor concentration.

Real-World Example: Solar Panels (eSewa’s Home Systems)

Solar cells use p-n junctions (Si doped with B and P). When sunlight excites electrons in the depletion region, they move to the n-side, creating a voltage → electricity.

sequenceDiagram
    participant Sunlight
    participant p-type
    participant n-type
    participant Circuit
    Sunlight->>p-type: Photon absorption
    p-type->>n-type: Electron-hole pair generation
    n-type->>Circuit: Electron flow (current)
    Circuit->>Load: Power delivery

4. Semiconductor Devices

a) p-n Junction Diode

• Forward Bias: Reduces barrier → current flows (e.g., LEDs, rectifiers).
• Reverse Bias: Increases barrier → negligible current (until breakdown).
• Applications:
  • eSewa’s Smart Meters: Use diodes to measure AC current direction.
  • Khalti’s Payment Systems: Diodes in voltage regulators for stable power.

b) Bipolar Junction Transistor (BJT)

• Structure: n-p-n or p-n-p.
• Operation: Current through base controls collector-emitter current.
• Example: Used in Ncell’s base stations for signal amplification.

Shows emitter, base, collector, and current directions. (Image: Osbert Joel for Electrical Classroom, CC BY-SA 4.0, via Wikimedia Commons)

c) Field-Effect Transistor (FET)

• MOSFET: Metal-Oxide-Semiconductor FET (used in all modern chips).
• Operation: Gate voltage controls channel conductivity.
• Example: Daraz’s servers use MOSFETs for low-power logic circuits.

5. Semiconductor Fabrication

Purification: Zone Refining

• Impure Si is melted in a narrow zone; impurities move to one end → 99.9999999% purity.
• Example: Used to make single-crystal Si ingots for chips.

Shows molten zone moving through a Si rod. (Image: Dbuckingham42, CC BY-SA 4.0, via Wikimedia Commons)

Single Crystal Growth (Czochralski Method)

• A seed crystal is dipped into molten Si and slowly pulled → large single crystal.
• Example: Intel/AMD processors start as single-crystal wafers.

IC Fabrication Steps

1. Wafer Preparation: Thin Si slices (0.5–1 mm).
2. Oxidation: Grow SiO₂ layer (insulator).
3. Photolithography: Pattern circuits using UV light.
4. Doping: Ion implantation for n/p regions.
5. Metallization: Add aluminum/copper for connections.

6. Electrical Conductivity of Semiconductors

Intrinsic Conductivity

$${\sigma }_i=n_{i}e({\mu }_e+{\mu }_h)$$ Where:

• $n_i$: Intrinsic carrier concentration.
• ${\mu }_e,{\mu }_h$: Electron/hole mobility (~1500 cm²/V·s for Si).

Extrinsic Conductivity (Doped)

For n-type: $${\sigma }_n=n_{0}e{\mu }_e=N_{d}e{\mu }_e$$ For p-type: $${\sigma }_p=p_{0}e{\mu }_h=N_{a}e{\mu }_h$$

Temperature Dependence

• Intrinsic: $\sigma \propto T^{3/2}{e}^{-E_g/2kT}$ → increases with T.
• Extrinsic: $\sigma \propto T^{-3/2}$ (at low T, carriers freeze out).

7. Applications in Nepal

Exam Tip

1. Band Theory: Always draw VB/CB diagrams for conductors/insulators/semiconductors. Memorize Eg values for Si (1.1 eV) and Ge (0.7 eV).
2. Doping: For n-type, $n_0=N_d$; for p-type, $p_0=N_a$. Assume full ionization unless stated.
3. Devices: Know the symbols for diodes, BJTs, and MOSFETs. Explain forward/reverse bias with current directions.
4. Fabrication: Zone refining → single crystal → photolithography → doping. Link to real chips (e.g., "This is how your phone’s processor is made").
5. Graphs: Plot $\sigma$ vs $T$ for intrinsic/extrinsic semiconductors. Label axes and trends.
6. Numerical Problems:
   • Calculate $n_i$ or $E_g$ using $n_i=\sqrt{N_c{N}_v}{e}^{-E_g/2kT}$.
   • Find conductivity $\sigma$ given $N_d$ or $N_a$.

Key Formula Summary: