Instruction Set Architecture (ISA) & Instruction Formats: Design, Types & Real-World Use

TAKEAWAYS:

• ISA defines how software interacts with hardware via instructions, formats, and addressing modes.
• Instruction formats (fixed vs. variable length) affect CPU efficiency and complexity.
• Addressing modes (immediate, direct, indirect) determine how operands are accessed.
• Real-world systems (e.g., WhatsApp’s encryption, Ncell’s billing) rely on ISA for speed and security.
• RISC vs. CISC trade-offs explain why smartphones use ARM (RISC) while PCs use x86 (CISC).
• Instruction cycles (fetch-decode-execute) are the heartbeat of CPU operation.

1. What is Instruction Set Architecture (ISA)?

ISA is the contract between hardware and software. It defines:

• The instructions a CPU can execute (e.g., ADD, LOAD, JUMP).
• The data types it supports (e.g., 8-bit, 16-bit, 32-bit integers).
• The registers available (e.g., PC, SP, AX).
• The memory addressing methods (e.g., direct, indirect).

Why it matters: Without ISA, programs couldn’t run—it’s the "language" CPUs understand. For example, when you send money via eSewa, the app’s code is compiled into ISA-specific instructions for your phone’s CPU.

classDiagram
    class ISA {
        +Instructions: ADD, SUB, LOAD, STORE, JUMP
        +Data Types: 8/16/32/64-bit integers, floats
        +Registers: PC, SP, AX, BX, etc.
        +Addressing Modes: Immediate, Direct, Indirect, etc.
    }
    class CPU {
        <<hardware>>
        Executes ISA instructions
    }
    class Program {
        <<software>>
        Written in high-level code, compiled to ISA
    }
    Program --> ISA : Compiled To
    ISA --> CPU : Executed By

2. Instruction Formats: How CPUs Understand Commands

Instructions are encoded in binary but follow a structured format. Two main types:

A. Fixed-Length Instructions (e.g., RISC)

• All instructions occupy the same number of bits (e.g., 32 bits).
• Simplifies decoding (CPU knows where each field starts).
• Example: ARM ISA (used in smartphones) uses 32-bit fixed-length instructions.

B. Variable-Length Instructions (e.g., CISC)

• Instructions vary in size (e.g., 1–15 bytes in x86).
• Allows complex operations in one instruction (e.g., MUL AX, BX).
• Example: x86 ISA (used in PCs) supports variable-length instructions.

Comparison Table:

Worked Example: Decoding an ARM Instruction Consider the ARM instruction: ADD R1, R2, R3 (Adds R2 and R3, stores result in R1). In binary (32-bit fixed format):

31-28 | 27-25 | 24-21 | 20-16 | 15-12 | 11-8 | 7-4 | 3-0
-------------------------------------------
  0101 |  000  |  001  |  010  |  011  |  000 | 0001

• Opcode (28-24): 010100 = ADD
• Dest (15-12): 0010 = R2
• Src1 (11-8): 011 = R3
• Src2 (7-4): 0001 = R1

3. Addressing Modes: How CPUs Find Data

Addressing modes determine how operands are specified in an instruction. Common types:

Real-World Example: WhatsApp Encryption When WhatsApp encrypts messages, it uses register indirect addressing to:

1. Load a key from memory into a register (LOAD R1, [R5]).
2. XOR the message with the key (XOR R1, R1, [R6]). This is faster than direct memory access because registers are closer to the CPU.

stateDiagram-v2
    [*] --> Fetch: Instruction from PC
    Fetch --> Decode: Opcode + Operands
    Decode --> AddressCalc: Determine operand location
    AddressCalc --> ReadOperand: From register/memory
    ReadOperand --> Execute: Perform operation
    Execute --> WriteBack: Store result
    WriteBack --> [*]
    state AddressCalc {
        [*] --> Immediate: Operand is literal
        [*] --> Direct: Operand is memory[addr]
        [*] --> Indirect: Operand is memory[reg]
        [*] --> Register: Operand is reg
    }

4. Instruction Cycle: The CPU’s Execution Loop

The instruction cycle is how a CPU fetches, decodes, and executes instructions. Steps:

1. Fetch: Get the next instruction from memory (address in PC).
2. Decode: Determine the instruction type (e.g., ADD, JUMP).
3. Execute: Perform the operation (e.g., arithmetic, memory access).
4. Writeback: Store the result (if needed).

With Interrupts (Real-World Example: Ncell Billing System) When a user tops up via Ncell’s app, the CPU handles:

• Normal cycle: Process payment.
• Interrupt: If the SIM card is removed, the CPU jumps to an interrupt handler to log the error.

sequenceDiagram
    participant CPU
    participant Memory
    participant InterruptController
    CPU->>Memory: Fetch (PC = 0x1000)
    Memory-->>CPU: Instruction (ADD R1, R2, R3)
    CPU->>CPU: Decode (ADD)
    CPU->>Memory: Read R2, R3
    Memory-->>CPU: Values (5, 3)
    CPU->>CPU: Execute (5 + 3 = 8)
    CPU->>Memory: Write R1 (8)
    InterruptController->>CPU: SIM Removed (Interrupt)
    CPU->>InterruptController: Acknowledge
    CPU->>Memory: Fetch (Interrupt Handler)

5. Instruction Types: What CPUs Can Do

Instructions are categorized by function:

Worked Example: Calculating Loan Interest (Nepal Bank) A bank’s system uses:

; Load principal (P), rate (R), time (T)
LOAD R1, [P]    ; R1 = 100,000 (NPR)
LOAD R2, [R]    ; R2 = 5 (5%)
LOAD R3, [T]    ; R3 = 1 (year)
; Calculate interest: I = P * R * T / 100
MUL R4, R1, R2  ; R4 = 100,000 * 5 = 500,000
MUL R5, R4, R3  ; R5 = 500,000 * 1 = 500,000
MOV R6, #100    ; R6 = 100
DIV R7, R5, R6  ; R7 = 500,000 / 100 = 5,000 (interest)
STORE [I], R7   ; Save to memory

6. Real-World Applications

A. eSewa: Secure Transactions

• Uses cryptographic instructions (e.g., AES-ENCRYPT) in fixed-length ISA (ARM).
• Addressing modes: Indirect addressing to load keys from secure memory.

B. Pathao: Ride Matching

• Control flow: Branches (JMP) to handle ride requests vs. cancellations.
• Data transfer: LOAD/STORE for GPS coordinates.

C. NTC: Traffic Light Control

• Interrupts: Sensors trigger CPU to switch lights (INT → JMP to handler).
• Timers: TIMER_LOAD instructions manage green/red durations.

Exam Tip

1. ISA vs. Microarchitecture:

   • ISA = what instructions exist (e.g., ADD).
   • Microarchitecture = how they’re implemented (e.g., pipelining).
   • Exam trick: Questions often ask for ISA examples (e.g., "List 3 ARM instructions").

2. Instruction Formats:

   • Draw a 32-bit ARM instruction and label fields (opcode, registers).
   • Compare fixed (RISC) vs. variable (CISC) in a table.

3. Addressing Modes:

   • Memorize 5 modes and give one example each (e.g., LOAD R1, [R2] for indirect).
   • Common mistake: Confusing direct (LOAD [addr]) vs. indirect (LOAD [reg]).

4. Instruction Cycle:

   • Draw the state diagram with interrupts (fetch-decode-execute-writeback).
   • Explain PC (Program Counter) updates in jumps.

5. Real-World Links:

   • Tie eSewa/Khalti to encryption instructions.
   • Tie Ncell billing to arithmetic/logic instructions.
   • Tie traffic lights to interrupts and timers.

Final Checklist for Full Marks: ✅ Define ISA and its components (instructions, registers, addressing). ✅ Compare fixed vs. variable-length instructions with examples. ✅ Explain 5 addressing modes with ARM/x86 examples. ✅ Draw the instruction cycle (with interrupts). ✅ Link to real systems (eSewa, Ncell, Pathao). ✅ Solve a worked example (e.g., loan calculation in assembly).