Embedded Systems ProgrammingUnit 18 min read
ARM Embedded Systems: Architecture & Applications
Unit 1 of Embedded Systems Programming introduces ARM architecture, its role in embedded systems, key components (CPU, memory hierarchy, peripherals), and real-world applications in Nepal and globally.
TAKEAWAYS:
- ARM is a 32/64-bit RISC architecture optimized for low power, cost-efficiency, and performance in embedded systems.
- The ARM Cortex-M family dominates microcontroller applications (e.g., NTC routers, Daraz logistics sensors).
- Memory hierarchy (registers → cache → RAM → flash) balances speed and cost in embedded systems.
- Peripherals (UART, SPI, ADC) enable communication and sensing in real-time systems.
- ARM-based SoCs (e.g., Raspberry Pi, Ncell base stations) power IoT and telecom infrastructure.
- Embedded Linux and RTOS (FreeRTOS) run on ARM cores for diverse applications.
1. Introduction to ARM Embedded Systems
ARM (Advanced RISC Machines) is a licensed architecture for microprocessors and microcontrollers, widely used in embedded systems due to its low power consumption, scalability, and cost-effectiveness. Unlike x86, ARM designs are optimized for real-time performance in resource-constrained devices.
1.1 Why ARM for Embedded Systems?
ARM excels in embedded applications because:
- Low power: Critical for battery-operated devices (e.g., NTC’s IoT sensors).
- Scalability: Cores range from 8-bit (Cortex-M0) to 64-bit (Cortex-A78).
- Licensing model: Companies pay for design rights, not per-chip royalties (unlike x86).
- Optimized instruction set: Reduces power usage in real-time tasks.
| Pin | Function | Description |
|---|---|---|
| PA0 | GPIO | General-purpose I/O |
| PB1 | UART TX/RX | Serial communication |
| VDD | Power Supply | 3.3V or 1.8V (depends on model) |
| GND | Ground | Reference voltage |
2. ARM Architecture Overview
ARM processors follow a load-store architecture (data moves via registers, not direct memory access). Key components:
2.1 Core Components
2.2 Memory Hierarchy
Embedded systems use a multi-level memory hierarchy to balance speed and cost:
| Level | Type | Size (Bytes) | Access Time | Example Use Case |
|---|---|---|---|---|
| L0 | Registers | 16–32 | ~1 cycle | Temporary data storage |
| L1 | Cache (SRAM) | 4KB–128KB | ~3–10 ns | Frequently accessed code/data |
| L2 | RAM (DRAM) | 128KB–1MB | ~50–100 ns | Runtime variables |
| L3 | Flash | 1MB–16MB | ~10–100 µs | Firmware/bootloader storage |
[Registers] →[1 cycle]→ [L1 Cache] →[3 ns]→ [RAM] →[50 ns]→ [Flash]
3. ARM Processor Families
ARM offers three main families for embedded systems:
| Family | Core Type | Word Size | Typical Use Case |
|---|---|---|---|
| Cortex-M | Microcontroller | 32-bit | IoT, sensors, motor control |
| Cortex-A | Application | 32/64-bit | Smartphones, tablets |
| Cortex-R | Real-time | 32-bit | Automotive, aerospace |
3.1 Cortex-M4: A Worked Example
The Cortex-M4 is popular in Nepal’s NTC routers and Daraz logistics trackers. Let’s trace its operation in a temperature sensor reading task:
Task: Read an ADC (Analog-to-Digital Converter) value and store it in RAM.
sequenceDiagram
participant Core as Cortex-M4
participant ADC as ADC Peripheral
participant RAM as RAM Memory
Core->>ADC: Enable ADC (GPIO config)
Core->>ADC: Start conversion
loop Wait for conversion
Core->>ADC: Check EOC (End-of-Conversion) flag
end
Core->>ADC: Read ADC value (DR register)
Core->>RAM: Store value in bufferCode Example (C for ARM):
#include <stdint.h>
#include "stm32f4xx.h" // STM32 uses Cortex-M4
uint16_t read_adc(void) {
ADC1->CR2 |= ADC_CR2_ADON; // Enable ADC
ADC1->CR2 |= ADC_CR2_SWSTART; // Start conversion
while (!(ADC1->SR & ADC_SR_EOC)); // Wait for EOC
return ADC1->DR; // Read result
}
Trace Table (Execution Steps):
| Step | Action | ADC_SR (EOC) | ADC_DR (Value) |
|---|---|---|---|
| 1 | Enable ADC | 0 | - |
| 2 | Start conversion | 0 | - |
| 3 | Poll EOC flag | 0 → 1 | - |
| 4 | Read DR register | 1 | 2500 (e.g.) |
4. ARM Peripherals
Peripherals extend ARM’s functionality without CPU overhead. Key types:
4.1 Communication Peripherals
| Peripheral | Description | Example Use Case |
|---|---|---|
| UART | Serial communication (TX/RX) | NTC’s router firmware |
| SPI | High-speed full-duplex | Daraz’s RFID tag reading |
| I2C | Multi-master, low-speed | Pathao’s GPS module |
[Master] ----[SCK]----[MISO]----[MOSI]----[Slave]
↑ ↑ ↑
CS Data Data
4.2 Sensor Interfaces
- ADC: Converts analog signals (e.g., temperature sensors in Ncell towers).
- DAC: Converts digital to analog (e.g., audio playback in embedded audio players).
Worked Example: ADC in NTC’s IoT Sensor NTC uses a Cortex-M0 to read ambient temperature via an LM35 sensor (0.1°C/°C resolution).
flowchart TD
A["ADC (STM32F0)] -->|Config| B["ADC1->CR2"]
B --> C["ADC1->CR2 |= ADC_CR2_ADON"]
C --> D["ADC1->CR2 |= ADC_CR2_SWSTART"]
D --> E["Wait for ADC_SR_EOC"]
E --> F["Read ADC1->DR"]
F --> G["Convert to °C: (ADC/4096)*1.8"]Trace for 25°C (LM35 output = 2.5V):
| Step | ADC_DR (Binary) | Decimal Value | °C Calculation |
|---|---|---|---|
| 1 | 0x09C4 | 2500 | (2500/4096)*1.8 ≈ 1.125V → 25°C |
5. ARM in Real-World Applications
In the Real World
NTC’s 5G Base Stations
- Idea: ARM Cortex-A72 (in NTC’s Huawei BTS) handles real-time signal processing and low-latency routing.
- Why ARM? High performance with low power consumption for outdoor deployment.
Daraz’s Logistics Tracking
- Idea: Cortex-M4 in LoRaWAN sensors tracks package location via GPS + ADC (battery voltage).
- Why ARM? Balances cost, power, and real-time updates for inventory management.
Khalti’s Payment Terminals
- Idea: Cortex-M0 processes EMV chip transactions with SPI for NFC communication.
- Why ARM? Ultra-low power for portable terminals.
6. ARM vs. Other Architectures
| Feature | ARM (Cortex-M) | AVR (Atmega) | PIC (18F) |
|---|---|---|---|
| Instruction Set | RISC | RISC | RISC |
| Word Size | 32-bit | 8/16-bit | 8/16-bit |
| Peripherals | Rich (DMA, CRC) | Limited | Moderate |
| Power Efficiency | High | Medium | Low |
| Typical Use | IoT, High-end MCUs | Low-cost MCUs | Legacy embedded |
7. Exam Tip
- Focus on:
- ARM’s RISC principles (load-store, pipelining).
- Memory hierarchy trade-offs (speed vs. cost).
- Peripheral configurations (UART, SPI, ADC) with code snippets.
- Real-world mapping: Always link ARM features to Nepalese examples (NTC, Daraz, Khalti).
- Common Pitfalls:
- Confusing Cortex-M (MCUs) with Cortex-A (SoCs).
- Forgetting to enable peripherals in code (e.g.,
ADC_CR2_ADON). - Misinterpreting ADC resolution (e.g., 12-bit ADC = 4096 steps).
Sample Exam Question: "Explain how an ARM Cortex-M4 processes an ADC reading for a temperature sensor in NTC’s IoT gateway. Include a code snippet and trace table."
Key Takeaway: ARM’s dominance in embedded systems stems from its scalability, power efficiency, and rich peripheral support. Mastering Cortex-M peripherals and memory hierarchy will give you an edge in exams and real-world projects like NTC’s 5G infrastructure or Daraz’s logistics tracking.
Based on the TU BSc CSIT syllabus for Embedded Systems Programming, unit 1.
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