ARM Processor: Core Architecture, Registers, Memory Map & Bus Interfaces

TAKEAWAYS:

• ARM uses a Harvard architecture with separate instruction/data buses, improving performance for embedded systems.
• The 37 general-purpose registers (R0–R15) include R13 (stack pointer), R14 (link register), and R15 (program counter).
• Memory-mapped I/O lets peripherals (UART, GPIO) appear as memory addresses, simplifying hardware access.
• The AMBA bus protocol (AHB/APB) standardizes communication between CPU, memory, and peripherals.
• Interrupts (FIQ/IRQ) enable real-time responses to external events, critical for embedded systems.
• Thumb mode (16-bit instructions) reduces code size, while ARM mode (32-bit) offers higher performance.

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## Core Architecture: Harvard vs. von Neumann
ARM processors predominantly use a **Harvard architecture**, where instruction and data memories are physically separate. This design allows simultaneous access to instructions and data, improving throughput—critical for embedded systems where latency matters.

```figure
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Why Harvard?

• Parallel access: Instructions and data can be fetched simultaneously.
• Reduced bottlenecks: No contention for a single memory bus.
• Energy efficiency: Smaller, faster memory interfaces.

Comparison Table

Register Set: The CPU’s Workspace

ARM processors have 37 registers, grouped into general-purpose, special-purpose, and status registers. These registers hold data, addresses, and control flags during execution.

General-Purpose Registers (R0–R12)

• R0–R3: Typically used for argument passing in function calls.
• R4–R12: Preserved across function calls (callee-saved).
• R13 (SP): Stack pointer, points to the top of the stack.
• R14 (LR): Link register, stores the return address for function calls.
• R15 (PC): Program counter, holds the address of the next instruction to execute.

Special-Purpose Registers

• CPSR (Current Program Status Register): Holds condition flags (N, Z, C, V) and processor mode bits.
• SPSR (Saved Program Status Register): Backup of CPSR during interrupt handling.
• MSR/MRS: Instructions to read/write CPSR/SPSR.

Example: Function Call and Return

void foo(int a, int b) {
    int c = a + b;  // R0 = a, R1 = b, R2 = c (temporary)
    return c;       // R0 = return value
}

Register State After foo(5, 3)

Memory Hierarchy and Memory-Mapped I/O

ARM systems use a memory hierarchy with different types of memory:

1. Flash Memory: Non-volatile storage for firmware (e.g., bootloader).
2. SRAM: Volatile, fast memory for variables and stack.
3. Peripherals: Devices like UART, GPIO, and timers mapped to memory addresses.

Memory-Mapped I/O

Peripherals are accessed like memory locations. For example:

• Writing to 0x40000000 might enable a GPIO pin.
• Reading from 0x40000004 might return a UART status.

Example: GPIO Toggle (STM32 ARM Cortex-M)

#define GPIOA_ODR 0x40010800  // GPIO Output Data Register address
void toggle_pin() {
    volatile uint32_t *gpio = (uint32_t *)GPIOA_ODR;
    *gpio ^= (1 << 5);  // Toggle bit 5 (PA5)
}

Memory State After Toggle

Bus Interfaces: AMBA AHB/APB

ARM uses the AMBA (Advanced Microcontroller Bus Architecture) protocol to connect the CPU to memory and peripherals. Two key buses:

1. AHB (Advanced High-performance Bus): High-speed bus for CPU, DMA, and high-bandwidth peripherals.
2. APB (Advanced Peripheral Bus): Low-power bus for peripherals like UART, I2C.

flowchart TD
    A["CPU Core"] -->|"AHB"| B["Memory Controller"]
    A -->|"AHB"| C["DMA Controller"]
    A -->|"APB"| D["UART"]
    A -->|"APB"| E["GPIO"]
    B -->|"APB Bridge"| D
    B -->|"APB Bridge"| E

Why AMBA?

• Standardization: Ensures compatibility across ARM-based systems.
• Scalability: Supports both high-speed (AHB) and low-power (APB) peripherals.
• Modularity: Peripherals can be added/removed without redesigning the bus.

Interrupts: Handling External Events

ARM supports two types of interrupts:

1. FIQ (Fast Interrupt Request): High-priority interrupt for time-critical tasks (e.g., audio processing).
2. IRQ (Interrupt Request): Standard interrupt for general-purpose events (e.g., button press).

stateDiagram-v2
  [*] --> IRQ
  IRQ --> SaveCPSR
  SaveCPSR --> SwitchMode
  SwitchMode --> JumpISR
  JumpISR --> ExecuteISR
  ExecuteISR --> RestoreCPSR
  RestoreCPSR --> [*]
  IRQ --> FIQ
  FIQ --> SaveCPSR
  SaveCPSR --> SwitchMode
  SwitchMode --> JumpISR
  JumpISR --> ExecuteISR
  ExecuteISR --> RestoreCPSR
  RestoreCPSR --> [*]
  note right of IRQ
    Standard Interrupt
  end
  note right of FIQ
    Fast Interrupt
  end

Interrupt Handling Steps

1. CPU finishes current instruction.
2. Saves CPSR to SPSR, switches to interrupt mode.
3. Jumps to interrupt vector (address stored in vector table).
4. Executes ISR (Interrupt Service Routine).
5. Restores CPSR, returns from interrupt.

flowchart LR
    A["Normal Execution"] -->|"Interrupt Occurs"| B["Save CPSR to SPSR"]
    B --> C["Switch to IRQ Mode"]
    C --> D["Jump to ISR"]
    D --> E["Execute ISR"]
    E --> F["Restore CPSR"]
    F --> G["Return from Interrupt"]

Example: Button Press ISR (STM32)

void EXTI0_IRQHandler(void) {
    if (EXTI->PR & EXTI_PR_PR0) {  // Check if button was pressed
        GPIOA->ODR ^= GPIO_ODR_5;   // Toggle LED
        EXTI->PR = EXTI_PR_PR0;     // Clear interrupt flag
    }
}

In the Real World

1. eSewa (Nepal):

   • Uses ARM-based microcontrollers (e.g., STM32) for memory-mapped I/O to read QR codes via GPIO/UART and process payments. The Harvard architecture ensures fast instruction/data access during transaction validation.

2. Pathao (Ride-Hailing App):

   • ARM Cortex-A series processors in smartphones handle interrupts for GPS updates (IRQ) and real-time navigation recalculations (FIQ for critical path adjustments). The AMBA bus connects the CPU to GPS peripherals efficiently.

3. NTC (Electricity Metering):

   • ARM-based meters use memory-mapped I/O to read voltage/current sensors (analog-to-digital converters mapped to memory addresses) and log consumption data to Flash. The Harvard architecture reduces latency during billing calculations.

Exam Tip

1. Diagrams are key: Draw the ARM Harvard architecture, register set, and memory map in exams. Label buses, registers, and memory regions precisely.
2. Memory-mapped I/O: Always show the address-decoding logic (e.g., how 0x40000000 maps to UART). Use a table to compare before/after states.
3. Interrupts: Explain the state transition (CPSR → SPSR, mode switch) and ISR flow in steps. Code snippets with comments score full marks.
4. AMBA vs. APB: Compare them in a table (speed, power, use cases). Mention the APB bridge in AHB systems.
5. Thumb vs. ARM mode: Know when to use each (e.g., Thumb for bootloader, ARM for performance-critical code). Show a code size comparison (e.g., ADD R0, R1, R2 vs. ADD R0, R1, R2 in Thumb).
6. Worked examples: Always trace register changes (e.g., SP after PUSH, PC after BX) and memory states (e.g., GPIO toggle). Use tables for clarity.

Practice Question: An ARM Cortex-M microcontroller has a stack pointer (R13) at 0x20001000. After executing PUSH {R4, LR}, what are the new SP value and the contents of the stack? Show the memory state in a table.