ARM Instruction Set: Data Processing, Branches, and Control Flow

Key Concepts and ARM Instruction Set Overview

The ARM instruction set is divided into three main categories:

1. Data Processing Instructions (e.g., arithmetic, logical, load/store)
2. Branch Instructions (e.g., conditional/unconditional jumps)
3. Control Flow Instructions (e.g., subroutine calls, returns)

ARM instructions are typically 32-bit (ARM mode) or 16-bit (Thumb mode). This unit focuses on ARM mode instructions, which are more powerful but less efficient in terms of code size.

1. Data Processing Instructions

Data processing instructions perform operations on registers or immediate values. They include:

• Arithmetic Instructions: ADD, SUB, MUL, DIV
• Logical Instructions: AND, ORR, EOR, NOT
• Load/Store Instructions: LDR, STR, LDM, STM
• Data Movement Instructions: MOV, MVN, CMP, CMN

1.1 Load/Store Architecture

ARM uses a load/store architecture, meaning only LDR/STR can access memory. All other operations work on registers.

Example: Loading and Storing Data

int x = 5;    // Assume 'x' is stored in memory at address 0x20000000
int y = 10;   // Assume 'y' is stored in memory at address 0x20000004
int sum;      // Assume 'sum' is stored in memory at address 0x20000008

ARM Assembly Equivalent:

LDR  R0, =0x20000000   @ Load address of 'x' into R0
LDR  R1, [R0]          @ Load value of 'x' (5) into R1
LDR  R2, =0x20000004   @ Load address of 'y' into R2
LDR  R3, [R2]          @ Load value of 'y' (10) into R3
ADD  R4, R1, R3        @ Add R1 (5) and R3 (10) → R4 (15)
STR  R4, =0x20000008   @ Store R4 (15) into 'sum'

Visual: Load/Store Operation

1.2 Arithmetic and Logical Instructions

• ADD: Adds two operands and stores the result in a destination register.

  ADD R0, R1, R2   @ R0 = R1 + R2
  

• SUB: Subtracts two operands.

  SUB R0, R1, R2   @ R0 = R1 - R2
  

• AND: Performs a bitwise AND.

  AND R0, R1, R2   @ R0 = R1 & R2
  

• ORR: Performs a bitwise OR.

  ORR R0, R1, R2   @ R0 = R1 | R2
  

Worked Example: Calculating Factorial (Iterative)

int factorial(int n) {
    int result = 1;
    for (int i = 1; i <= n; i++) {
        result *= i;
    }
    return result;
}

ARM Assembly Equivalent (Simplified):

factorial:
    MOV R2, #1       @ Initialize result = 1 (R2)
    MOV R3, #1       @ Initialize i = 1 (R3)
loop:
    CMP R3, R0       @ Compare i (R3) with n (R0)
    BGT end_loop     @ If i > n, exit loop
    MUL R2, R2, R3   @ result *= i (R2 = R2 * R3)
    ADD R3, R3, #1   @ i++
    B loop           @ Repeat
end_loop:
    MOV R0, R2       @ Return result (R0)
    BX LR            @ Return from subroutine

Visual: Factorial Calculation (State After Each Step)

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2. Branch Instructions

Branch instructions alter the flow of execution based on conditions or unconditionally.

2.1 Conditional Branches

ARM supports 16 conditional branches (e.g., BEQ, BNE, BGT, BLT). These check the condition flags (N, Z, C, V) set by previous instructions.

Example: Checking if Two Numbers are Equal

CMP R1, R2       @ Compare R1 and R2
BEQ equal        @ Branch if equal (Z flag set)
BNE not_equal    @ Branch if not equal
equal:
    MOV R0, #1   @ Set R0 = 1 (true)
    B end
not_equal:
    MOV R0, #0   @ Set R0 = 0 (false)
end:
    BX LR

Visual: Conditional Branch (BEQ/BNE)

2.2 Unconditional Branches

• B: Branch to a label.

  B label         @ Unconditional branch
  

• BL: Branch with link (saves return address in LR).

  BL subroutine   @ Call subroutine
  

Worked Example: Simple Menu-Driven Program

start:
    MOV R0, #1     @ Menu option 1
    BL print_menu
    CMP R0, #1
    BEQ option1
    CMP R0, #2
    BEQ option2
    B start        @ Repeat if invalid
option1:
    BL task1
    B start
option2:
    BL task2
    B start

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3. Control Flow Instructions

Control flow instructions manage program flow, including:

• BL/BLX: Branch with link (subroutine calls).
• BX/BLX: Branch to address in register (returns from subroutine).
• SWI: Software interrupt (used for OS calls).

Example: Subroutine Call and Return

main:
    MOV R0, #5
    BL square      @ Call square subroutine
    BX LR          @ Return from main
square:
    MUL R0, R0, R0 @ R0 = R0 * R0
    BX LR          @ Return to caller

Visual: Subroutine Call Stack

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In the Real World

1. eSewa (Nepal):

   • Uses ARM-based microcontrollers in its payment terminals to process transactions securely. The ARM instruction set handles real-time data validation (e.g., CMP for checking card PINs) and encryption (using logical instructions like EOR for XOR operations in cryptography).

2. Pathao (Ride-Hailing App):

   • ARM processors in driver smartphones and server backends use branch instructions (BEQ, BNE) to route passengers efficiently. For example:

     CMP R1, #available_driver  @ Check if driver is available
     BEQ assign_ride            @ If yes, assign ride
     B find_next_driver         @ Else, search for another
     

   • The app’s navigation system relies on arithmetic instructions (ADD, SUB) to calculate distances and optimize routes.

3. Smart Meters (NTC, Nepal):

   • ARM-based energy meters use load/store instructions (LDR, STR) to read sensor data (e.g., voltage, current) from memory-mapped I/O registers. For example:

     LDR R1, =0x40000000   @ Load address of voltage sensor
     LDR R2, [R1]          @ Read voltage value (e.g., 220V)
     STR R2, =0x20000000   @ Store in memory for logging
     

4. Bank ATMs (Nepal):

   • ARM processors in ATMs use conditional branches to validate transactions. For example:

     CMP R0, #valid_pin    @ Compare entered PIN
     BNE deny_access       @ If invalid, deny access
     BL process_withdrawal @ Else, proceed
     

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Exam Tip

1. Understand the Syntax:

   • ARM instructions are 3-operand (e.g., ADD Rd, Rn, Rm). Memorize the order: destination, source1, source2.
   • Example: ADD R1, R2, R3 (R1 = R2 + R3), not ADD R2, R1, R3.

2. Condition Flags:

   • Always check which flags (N, Z, C, V) are set by CMP/SUB before using conditional branches (BEQ, BNE, BGT, etc.).
   • Example: CMP R1, R2 sets Z=1 if equal, then BEQ label works.

3. Load/Store Architecture:

   • Only LDR/STR access memory. All other operations are register-based. This is a common exam question!

4. Worked Examples:

   • For questions involving loops or conditionals, trace the state of registers after each instruction (like the factorial example above).
   • Example question: "Write ARM code to check if a number in R0 is even. Use CMP and BEQ."

     AND R1, R0, #1   @ Check LSB
     BEQ even         @ If LSB=0, even
     B odd            @ Else, odd
     

5. Practical Applications:

   • Expect questions linking ARM instructions to real-world scenarios (e.g., "How would you use BL in a smart home system?").
   • Example answer: "BL calls a subroutine to process sensor data (e.g., temperature) from an ARM-based microcontroller in a smart thermostat."

6. Common Pitfalls:

   • Forgetting to update the link register (LR) before returning from a subroutine (BX LR).
   • Misusing MOV vs. ADD: MOV R0, #5 sets R0=5, while ADD R0, R0, #5 adds 5 to R0’s current value.

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TAKEAWAYS:

• ARM instructions are 32-bit (ARM mode) and follow a load/store architecture.
• Data processing instructions (ADD, SUB, AND, LDR, STR) manipulate registers and memory.
• Branch instructions (B, BL, BEQ, BNE) control program flow based on conditions.
• Control flow (BL, BX) manages subroutine calls and returns.
• Real-world applications include payment terminals (eSewa), ride-hailing (Pathao), and smart meters (NTC).
• Always trace register states and check condition flags in exam questions.