Sequential Logic: Flip-Flops, Counters & State Machines

TAKEAWAYS:

• Flip-flops store state: SR, D, T, and JK flip-flops are the building blocks of sequential circuits, each with unique input-output behavior and timing constraints.
• Counters count: Ripple counters (asynchronous) and synchronous counters use flip-flops to count pulses, with synchronous counters being faster and more reliable.
• State machines model behavior: Mealy and Moore machines use flip-flops to implement finite state machines (FSMs) for tasks like protocol control or traffic light sequencing.
• Timing is critical: Setup and hold times ensure reliable data transfer between flip-flops and combinational logic.
• Real-world applications: From eSewa transaction counters to Ncell call duration timers, sequential circuits power everyday digital systems.

1. Introduction to Sequential Logic Circuits

Sequential logic circuits remember past inputs (unlike combinational circuits) and produce outputs based on both current and previous inputs. They rely on memory elements (flip-flops) and clock signals to synchronize operations.

Key Features:

• State-dependent: Output depends on current inputs and past states.
• Clock-driven: Operations synchronized by a clock signal (edge-triggered or level-sensitive).
• Applications: Counters, registers, memory units, state machines, and digital clocks.

2. Flip-Flops: The Memory Elements

Flip-flops are bistable multivibrators that store a single bit of data. They come in four primary types:

A. SR (Set-Reset) Flip-Flop

• Inputs: S (Set), R (Reset)
• Behavior:
  • S=1, R=0: Set (Q=1)
  • S=0, R=1: Reset (Q=0)
  • S=1, R=1: Forbidden (invalid state)
  • S=0, R=0: Hold previous state (latch behavior)
• Truth Table:

  | S | R | Q(n+1) | Q̅(n+1) |
  |---|---|--------|---------|
  | 0 | 0 | Q(n)   | Q̅(n)   |
  | 0 | 1 | 0      | 1       |
  | 1 | 0 | 1      | 0       |
  | 1 | 1 | X      | X       |
  

B. D (Delay) Flip-Flop

• Inputs: D (Data)
• Behavior: Output Q follows D after the clock edge.
  • Q(n+1) = D
• Truth Table:

  | CLK | D | Q(n+1) |
  |-----|---|--------|
  | ↑    | 0 | 0      |
  | ↑    | 1 | 1      |
  

C. T (Toggle) Flip-Flop

• Inputs: T (Toggle)
• Behavior: Toggles Q on each clock pulse if T=1.
  • Q(n+1) = Q(n) ⊕ T
• Truth Table:

  | CLK | T | Q(n+1) |
  |-----|---|--------|
  | ↑    | 0 | Q(n)   |
  | ↑    | 1 | Q̅(n)  |
  

D. JK Flip-Flop

• Inputs: J, K (enhanced SR flip-flop)
• Behavior:
  • J=1, K=0: Set (Q=1)
  • J=0, K=1: Reset (Q=0)
  • J=1, K=1: Toggle (Q changes state)
  • J=0, K=0: Hold previous state
• Truth Table:

  | J | K | Q(n+1) |
  |---|---|--------|
  | 0 | 0 | Q(n)   |
  | 0 | 1 | 0      |
  | 1 | 0 | 1      |
  | 1 | 1 | Q̅(n)  |
  

3. Flip-Flop Excitation Tables

Excitation tables determine the required inputs (e.g., J, K, or D) to achieve a desired state transition.

Example: JK Flip-Flop Excitation Table

For a transition from Q(n) = 0 to Q(n+1) = 1:

• J = 1, K = X (don’t care, can be 0 or 1).

| Q(n) | Q(n+1) | J | K |
|------|---------|---|---|
|  0   |   0     | 0 | X |
|  0   |   1     | 1 | X |
|  1   |   0     | X | 1 |
|  1   |   1     | X | 0 |

4. Counters: Sequential Logic in Action

Counters are sequential circuits that increment or decrement on clock pulses. Two main types:

A. Ripple (Asynchronous) Counters

• Operation: Each flip-flop triggers the next (cascade effect).
• Disadvantages:
  • Slow (propagation delay accumulates).
  • Outputs change at different times (glitches).
• Example: 3-bit ripple counter using T flip-flops.

B. Synchronous Counters

• Operation: All flip-flops triggered simultaneously by the clock.
• Advantages:
  • Faster (no propagation delay).
  • Cleaner outputs (no glitches).
• Design Steps:
  1. Determine the modulus (e.g., MOD-10 for decimal counting).
  2. Use JK flip-flops with appropriate excitation tables.
  3. Connect flip-flops to reset at the desired count (e.g., 10 for MOD-10).

Worked Example: MOD-10 Synchronous Counter Problem: Design a MOD-10 counter using JK flip-flops. Solution:

1. State Diagram:

2. Excitation Table:

   | Q2Q1Q0 | Q2(n+1)Q1(n+1)Q0(n+1) | J2 K2 | J1 K1 | J0 K0 |
   |--------|------------------------|-------|-------|-------|
   | 000    | 001                    | 0 X   | 0 X   | 1 X   |
   | 001    | 010                    | 0 X   | 1 X   | 1 X   |
   | 010    | 011                    | 0 X   | 0 X   | 1 X   |
   | 011    | 100                    | 1 X   | 1 X   | 1 X   |
   | 100    | 101                    | 0 X   | 0 X   | 1 X   |
   | 101    | 110                    | 0 X   | 1 X   | 1 X   |
   | 110    | 111                    | 0 X   | 0 X   | 1 X   |
   | 111    | 000                    | 1 X   | 1 X   | 1 X   |
   

3. K-Map Simplification (for J2, K2, etc.):
   • J2 = Q1Q0 (groups states 011 and 111).
   • K2 = Q1̅Q0̅ (groups states 000 and 100).
4. Final Circuit:

Timing Diagram:

5. Real-World Applications of Sequential Logic

A. eSewa Transaction Counters

• Application: eSewa uses synchronous counters to track transaction IDs.
• How it works:
  • Each transaction increments a MOD-N counter (where N is the max transaction limit).
  • Counters ensure unique IDs and prevent duplicates.

B. Ncell Call Duration Timer

• Application: Ncell’s billing system uses JK flip-flops to measure call duration.
• How it works:
  • A clock-driven counter increments every second.
  • When the call ends, the counter value is read to calculate billing.

C. Traffic Light Controller (Moore Machine)

• Application: Kathmandu’s traffic lights use finite state machines (FSMs).
• How it works:
  • States: Red → Green → Yellow → Red.
  • Transitions: Triggered by timers (sequential logic).
  • Outputs: Lights change based on current state (Moore machine).

6. Designing Sequential Circuits from State Diagrams

Steps:

1. Draw the state diagram (e.g., for a binary sequence detector).
2. Assign binary codes to each state (e.g., 00, 01, 10, 11).
3. Write the excitation table (inputs needed for each transition).
4. Simplify using K-Maps (if combinational logic is involved).
5. Implement with flip-flops (JK or D flip-flops preferred).

Example: Binary Sequence Detector (101)

stateDiagram-v2
  [*] --> S0: 00
  S0 --> S1: 1
  S1 --> S2: 0
  S2 --> S3: 1
  S3 --> S0: 0
  S3 --> [*]: 1

7. Exam Tip: How to Score Full Marks

1. For counter design:

   • Always show the state diagram, excitation table, and simplified logic.
   • Label all flip-flops and connections clearly.
   • Include a timing diagram for asynchronous counters.

2. For flip-flop questions:

   • Draw the logic diagram (NAND/NAND or NOR/NOR implementation).
   • Provide the truth table and characteristic equation.

3. For state machines:

   • Distinguish between Mealy (output depends on inputs) and Moore (output depends only on state).
   • Show next-state and output equations.

4. Common pitfalls:

   • Forgetting to reset the counter (e.g., MOD-10 must return to 000 after 111).
   • Ignoring don’t care conditions in excitation tables.
   • Mislabeling clock edges (rise vs. fall).

8. Summary Table: Flip-Flop Comparison

9. Practice Problems (Exam-Style)

1. Design a MOD-6 synchronous counter using JK flip-flops.
   • Show state diagram, excitation table, and circuit.
2. Implement a binary up/down counter using D flip-flops.
   • Use a control input to switch between up and down modes.
3. Design a sequential circuit for the sequence "1101" using a Moore machine.
   • Draw the state diagram and implement with JK flip-flops.