ISA, Addressing Modes & Instruction Formats: How CPUs Execute Code

TAKEAWAYS:

• ISA defines how a CPU interacts with software (instructions, data types, registers) but hides hardware details.
• Addressing modes (immediate, direct, indirect, indexed) determine how operands are located in memory or registers.
• Instruction formats (0-, 1-, 2-, 3-address) trade off code size, speed, and hardware complexity.
• Real-world impact: ISAs power apps like WhatsApp (ARM ISA for mobile encryption) and eSewa (x86_64 for transaction processing).
• Trade-offs: More addressing modes → more flexibility but slower decoding; more address fields → more hardware but less code density.
• Exam focus: Compare addressing modes, evaluate expressions in different formats, and explain ISA’s role in CPU design.

1. Instruction Set Architecture (ISA): The CPU’s Contract with Software

ISA is the interface between hardware (CPU) and software (programs). It specifies:

• Instructions: What operations the CPU can perform (e.g., ADD, LOAD, JUMP).
• Data types: How numbers, text, and memory are represented (e.g., 32-bit integers, floating-point).
• Registers: Fast storage locations inside the CPU (e.g., AX, PC, SP).
• Addressing modes: How to specify operands (memory vs. registers).
• Instruction formats: How instructions are encoded in binary (e.g., 32-bit vs. variable-length).

Why ISA Matters

• Abstraction: Hides hardware complexity (e.g., a MOV instruction works the same on Intel or ARM CPUs if they support the same ISA).
• Performance: Different ISAs optimize for speed (CISC, like x86) or simplicity (RISC, like ARM).
• Compatibility: Software written for an ISA runs only on CPUs supporting it (e.g., Windows on x86, Android on ARM).

Real-World Example: WhatsApp on Your Phone

• ISA Used: ARM (e.g., ARMv8 for modern smartphones).
• How It Works:
  • When you send a message, the app’s code (compiled for ARM ISA) uses instructions like ADD (to calculate memory addresses) and STORE (to encrypt data).
  • The ARM CPU’s decoder translates these instructions into control signals for the ALU (Arithmetic Logic Unit).
  • Addressing modes: The app uses register indirect mode to access memory locations for encryption keys.

2. Components of an Instruction

Every instruction has two key parts:

1. Opcode (Operation Code): Specifies the operation (e.g., ADD, SUB, JMP).
2. Operands: Data or memory locations the instruction acts on.

Instruction Format Example: x86 ADD Instruction

| 7 bits | 3 bits | 3 bits | 8 bits | 8 bits | 16 bits |
|--------|--------|--------|--------|--------|---------|
| Opcode | ModRM | SIB    | Displacement | Immediate |

• Opcode (7 bits): Defines the operation (e.g., 0000000 for ADD).
• ModRM (3 bits): Specifies registers and addressing modes.
• Displacement/Immediate: Values or memory offsets.

3. Addressing Modes: How to Find Operands

Addressing modes determine how the CPU locates an operand. There are 7 primary modes (varies by ISA; we’ll cover the most common):

Comparison Table: Addressing Modes

Visual: Addressing Mode Examples

+-------------------+       +-------------------+
| Instruction: ADD  |       | Instruction: ADD  |
| AX, [BX + 4]      |       | AX, #5            |
+--------+----------+       +--------+----------+
         |                          |
         v                          v
+-------------------+       +-------------------+
| Register BX: 2000|       | Immediate: 5      |
+-------------------+       +-------------------+
         |                          |
         v                          v
+-------------------+       +-------------------+
| Memory [2004]: 10 |       | Register AX: 3    |
+-------------------+       +-------------------+
         |                          |
         v                          v
| AX = 10 + 3 = 13 |       | AX = 3 + 5 = 8    |
+-------------------+       +-------------------+

• Left (Base + Displacement): AX = [BX + 4] → AX = [2000 + 4] = 10, then AX = AX + 10 = 13.
• Right (Immediate): AX = AX + 5 directly.

4. Instruction Formats: Trading Off Code Size and Hardware

Instructions can be encoded in 0-, 1-, 2-, or 3-address formats, each with trade-offs:

Comparison Table: Instruction Formats

Real-World Example: eSewa Transaction Processing

• ISA Used: x86_64 (for servers) or ARM (for mobile).
• Instruction Format: Mostly 3-address (e.g., MOV EAX, [ESI], ECX to transfer funds).
• Why?:
  • Flexibility: Complex transactions need multiple operands (e.g., balance = balance - amount).
  • Performance: Modern CPUs optimize for 3-address formats with pipelining (Unit 7).

5. Evaluating Expressions in Different Formats

Problem: Evaluate X = (M * N) + (P * Q) using:

1. 3-address instructions (e.g., ADD, MUL with 3 operands).
2. 2-address instructions (e.g., ADD AX, BX; needs a temporary register).
3. 1-address instructions (accumulator-based, e.g., LD AX, M).
4. 0-address instructions (stack-based, e.g., PUSH M, MUL).

Solution: 3-Address Format (x86-like)

sequenceDiagram
    participant CPU
    participant Memory
    CPU->>Memory: Load M into AX
    CPU->>Memory: Load N into BX
    CPU->>CPU: MUL AX, BX (AX = M * N)
    CPU->>Memory: Store AX to Temp1
    CPU->>Memory: Load P into AX
    CPU->>Memory: Load Q into BX
    CPU->>CPU: MUL AX, BX (AX = P * Q)
    CPU->>CPU: ADD AX, Temp1 (AX = (M*N) + (P*Q))
    CPU->>Memory: Store AX to X

Solution: 2-Address Format (PDP-11-like)

1. MUL R1, M, N → R1 = M * N
2. MUL R2, P, Q → R2 = P * Q
3. ADD R1, R2 → R1 = (M*N) + (P*Q)
4. MOV X, R1 → Store result.

Solution: 1-Address Format (Accumulator)

1. LD M → AX = M
2. LD N → AX = N
3. MUL → AX = M * N
4. ST Temp1 → Store AX to Temp1
5. LD P → AX = P
6. LD Q → AX = Q
7. MUL → AX = P * Q
8. LD Temp1 → AX = M*N
9. ADD → AX = (M*N) + (P*Q)
10. ST X → Store result.

Solution: 0-Address Format (Stack)

1. PUSH M
2. PUSH N
3. MUL → M * N pushed
4. PUSH P
5. PUSH Q
6. MUL → P * Q pushed
7. ADD → (M*N) + (P*Q) pushed
8. POP X → Store result.

6. Real-World Applications

Example 1: Daraz Order Processing (Queue Management)

• ISA Used: x86_64 (server CPUs) or ARM (mobile app).
• Addressing Mode: Register Indirect for dynamic order queues.
  • Code uses LOAD [BX] to fetch the next order ID from a memory queue.
  • ADD BX, #4 increments the pointer to the next order.
• Instruction Format: 3-address for complex logic (e.g., CMP [BX], #PAID to check order status).

Example 2: NTC Traffic Light Control (Timers and Jumps)

• ISA Used: Embedded microcontrollers (e.g., ARM Cortex-M).
• Addressing Mode: Relative for jumps between traffic light states.
  • JMP GreenLight (if timer expired).
  • JMP RedLight (if pedestrian button pressed).
• Instruction Format: 2-address for simplicity (e.g., MOV Timer, #30 to set a 30-second countdown).

Example 3: NEPSE Stock Trading (Floating-Point Math)

• ISA Used: x86_64 (with FPU for floating-point).
• Addressing Mode: Base + Displacement for stock price arrays.
  • LOAD FP0, [BX + SI*4] to access the price of stock SI in array [BX].
• Instruction Format: 3-address for financial calculations (e.g., MUL FP0, FP1, FP2 for price = quantity * rate).

7. ISA Design Trade-Offs

IMAGE: x86 vs. ARM Instruction Encoding

Exam Tip: How to Score Full Marks

1. Definitions:

   • ISA: "The interface between hardware and software defining instructions, data types, and addressing modes."
   • Addressing Mode: "A rule for locating an operand in memory or registers."

2. Diagrams:

   • Always draw memory/register diagrams for addressing modes (e.g., show [BX + 4] pointing to memory).
   • For instruction formats, use bit-field diagrams (like the x86 ADD example above).

3. Worked Examples:

   • Must show: Step-by-step evaluation of expressions (like X = (M*N) + (P*Q)).
   • Label registers/memory clearly (e.g., "Load M into AX").

4. Real-World Links:

   • Connect addressing modes to eSewa (register indirect for transactions) or Daraz (base + displacement for orders).
   • Mention CISC vs. RISC in the context of Intel (x86) vs. Apple (ARM).

5. Common Pitfalls:

   • Don’t confuse: Addressing mode (how to find data) vs. instruction format (how data is encoded).
   • Don’t forget: Stack machines (0-address) use reverse Polish notation (e.g., 3 4 + for 3 + 4).

Summary Checklist

Before the exam, ensure you can:

• Define ISA and list its 5 components.
• Draw and explain all 7 addressing modes with memory/register diagrams.
• Evaluate an expression in all 4 instruction formats (0-, 1-, 2-, 3-address).
• Compare CISC vs. RISC with examples (x86 vs. ARM).
• Link 2 real-world apps (e.g., WhatsApp, eSewa) to ISA concepts.